Design for Embedded Reconfigurable Systems Using MORPHEUS Platform

  • Paul Brelet
  • Philippe Millet
  • Arnaud Grasset
  • Philippe Bonnot
  • Frank Ieromnimon
  • Dimitrios Kritharidis
  • Nikolaos S. Voros
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 105)


This chapter is related to the paper “System Level Design for Embedded Reconfigurable Systems using MORPHEUS platform” (Brelet et al. (2010) System level design for embedded reconfigurable systems using MORPHEUS platform). It presents a novel approach for designing embedded reconfigurable systems. Reconfigurable systems bring a significant importance for their highly attractive mix of performance density, power efficiency and flexibility. In this chapter, we present a toolset that abstracts the heterogeneity and benefits of a dynamically reconfigurable heterogeneous platform called MORPHEUS (Voros et al. (2009) Dynamic system reconfiguration in heterogeneous platforms, the MORPHEUS approach. This platform consists of a System-on-Chip made of a regular system infrastructure hosting different kinds of heterogeneous reconfigurable engines accelerating some operations. Integrated mechanisms simplify the utilization of these reconfigurable accelerators at design time and minimize the time to fetch and reconfigure a function dynamically at run time. Implementing an application on the platform is made easier and faster by a comprehensive design environment. Industrial use cases from various application domains are also presented and used to evaluate the performance of the platform and assess the MORPHEUS concept.


Reconfigurable computing Systems-on-Chip Heterogeneous architectures Dynamic reconfiguration Toolset Embedded systems 



The authors would like to thank all the partners of the project consortium who were involved in studying and providing the required technologies, specifying the requirements and assessing the results. This research was partially funded by the European Community’s 6th Framework Program.


  1. 1.
    Brelet P, Grasset A, Bonnot P, Ieromnimon F, Kritharidis D, Voros NS (2010) System level design for embedded reconfigurable systems using MORPHEUS platform. In: Proceedings of the 2010 IEEE annual symposium on VLSI 5 July 2010. ISVLSI. IEEE computer society, Washington, DC, pp 500–505.
  2. 2.
    Voros N, Rosti A, Hübner M (2009) Dynamic system reconfiguration in heterogeneous platforms, the MORPHEUS approach. Springer, BerlinCrossRefGoogle Scholar
  3. 3.
    Mair H, Wang A, Gammie G, Scott D, Royannez P, Gururajarao S, Chau M, Lagerquist R, Ho L, Basude M, Culp N, Sadate A, Wilson D, Dahan F, Song J, Carlson B, Ko U. A 65-nm mobile multimedia applications processor with an adaptive power management scheme to compensate for variations. Digital Signal Processing, pp 8–9Google Scholar
  4. 4.
    Clark L, Hoffman E, Miller J, Biyani M, Strazdus S, Morrow M, Velarde K, Yarch M (2001) An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE J Solid State Circ 36:1599–1608CrossRefGoogle Scholar
  5. 5.
    Lenormand E, Edelin G (2003) An industrial perspective: pragmatic high-end signal processing environment at Thales. In: Proceedings of the 3rd international workshop on synthesis, architectures, modeling and simulation (SAMOS)Google Scholar
  6. 6.
    Gast N, Gaujal B (2010) A mean field approach for optimization in discrete time. J Discrete Event Dyn SystGoogle Scholar
  7. 7.
    Klein F, Leao R, Araujo G, Santos L, Azevedo R (2007) A multi-model power estimation engine for accuracy optimization. ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and designGoogle Scholar
  8. 8.
    Muhammad R, Apvrille L, Pacalet R (2008) Evaluation of ASIPs design with LISATek: Springer Volume 5114/2008Google Scholar
  9. 9.
    Clarke P (2002) Chess/checkers tool flow brings verification into play. EETimes articleGoogle Scholar
  10. 10.
    SystemC Modeling, Synthesis, and Verification in Catapult C, Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, Oregon, USA. [online] Available: Scholar
  11. 11.
    Mitrionics (2008) Low power hybrid computing for efficient software acceleration. White paperGoogle Scholar
  12. 12.
    Pellerin D, Thibault EA (2005) Practical FPGA programming in C, Prentice HallGoogle Scholar
  13. 13.
    University of Newcastle upon Tyne (2003) Matlab/Simulink tutorialGoogle Scholar
  14. 14.
    Campbell SL, Nikoukhah R (2004) Auxiliary signal design for failure detection. Princeton University Press, PrincetonMATHGoogle Scholar
  15. 15.
    Bergmann J, McCoy D (2004) Sourcery VSIPL++ HPEC benchmark performance. HPCMP-UGC '06 Proceedings of the HPCMP Users Group ConferenceGoogle Scholar
  16. 16.
    Snir M, Otto S, Huss-Lederman S, Walker D, Dongarra J, MPI the complete reference. [online] Available: Scholar
  17. 17.
    Chapman B, Jost G, van der Pas R, Kuck DJ (2008) Using openMP: portable shared memory parallel programming. MIT Press, CambridgeGoogle Scholar
  18. 18.
    Fowler M (2008) UML distilled: a brief guide to the standard object modeling language. Published September 25th 2003 by Addison-Wesley ProfessionalGoogle Scholar
  19. 19.
    Weilkiens T (2006) Systems engineering with SysML/UML: modeling analysis, design. Hüthing, HeidelbergMATHGoogle Scholar
  20. 20.
    PACT XPP Technologies (2005) PACT software design system XPP-IIb (PSDS XPP-IIb)—programming tutorial. Version 3.2, November 2005Google Scholar
  21. 21.
    Stitt G, Grattan B, Villarreal J, Vahid F (2002) Using on-chip configurable logic to reduce embedded system software energy. IEEE symposium on field-programmable custom computing machines, Napa Valley, USAGoogle Scholar
  22. 22.
    Baron M (2004) M2000’s spherical FPGA cores. MicroProcessor report, Dec 2004Google Scholar
  23. 23.
    Coppola M, Locatelli R, Maruccia G, Pieralisi L, Scandurra A (2004) Spidergon: a novel on-chip communication network. Proceedings of the international symposium on system-on-chip, pp 16–18Google Scholar
  24. 24.
    Whitty S, Ernst R (2008) A bandwidth optimized SDRAM controller for the MORPHEUS reconfigurable architecture. In: Proceedings of the IEEE parallel and distributed processing symposium (IPDPS)Google Scholar
  25. 25.
    Amar A, Boulet P, Dumont P, Projection of the array-OL specification language onto the Kahn process network computation model. [online] Available: Scholar
  26. 26.
    CRITICALBLUE (2005) Boosting software processing performance with co-processor synthesis. White paperGoogle Scholar
  27. 27.
    Whitty S, Sahlbach H, Hurlburt B, Putzke-Röming W, Ernst R (2010) Application-specific memory performance of a heterogeneous reconfigurable architecture. In: Proceedings of design, automation and test in Europe (DATE)Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Paul Brelet
    • 1
  • Philippe Millet
    • 1
  • Arnaud Grasset
    • 1
  • Philippe Bonnot
    • 1
  • Frank Ieromnimon
    • 2
  • Dimitrios Kritharidis
    • 2
  • Nikolaos S. Voros
    • 3
  1. 1.Thales Research and TechnologyNeuilly-sur-SeineFrance
  2. 2.INTRACOM Telecom Solutions S.AAthensGreece
  3. 3.Department of Telecommunication Systems and Networks (consultant to Intracom Telecom Solutions S.A)Technological Educational Institute of MesolonghiAthensGreece

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