Off-Chip SDRAM Access Through Spidergon STNoC

  • Khaldon Hassan
  • Marcello Coppola
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 105)


External memory access in MPSoCs becomes more challenging with the growing requirements for high bandwidth and low latency. We propose a novel method for optimizing external memory access in term of latency for NoC-based MPSoCs. Our approach considers the off-chip memory access within a system approach: from the initiators to the memory modules through the NoC-based interconnect. We couple QoS of both NoC and memory scheduler in order to guarantee continued services throughout the request and the response paths, between the masters and the SDRAM modules. We study the influence of low-priority requests over high-priority requests. We also analyze the influence of the number of the conflict points inside the NoC over high-priority requests latency. We compare the use of virtual channels with the physical direct connection to map latency-sensitive IPs requests towards the memory subsystem, and demonstrate that both solutions are equivalent in term of memory access latency.



We would like to express our sincere gratitude to Prof. Frédéric Pétrot of TIMA Laboratory in Grenoble for offering his tremendous experience in the field to promote this work.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.STMicroelectronicsGrenobleFrance

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