SUT-RNS Forward and Reverse Converters

  • E. Vassalos
  • D. Bakalis
  • H. T. Vergos
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 105)


Stored Unibit Transfer (SUT) has recently been considered as a redundant high-radix encoding for the channels of a Residue Number System (RNS) that can improve the efficiency of conventional redundant RNS. In this work we propose modulo 2 n  ± 1 forward and reverse converters for the SUT-RNS encoding. The proposed converters are based on parallel-prefix binary or modulo adders and are therefore highly efficient.


Residue Number System Arithmetic Circuit Binary Encode Parallel Prefix Input Operand 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Ananda Mohan PV (2002) Residue number systems: algorithms and architectures. Kluwer, NetherlandsGoogle Scholar
  2. 2.
    Omondi A, Premkumar B (2007) Residue number systems: theory and implementation. Imperial College Press, LondonzbMATHCrossRefGoogle Scholar
  3. 3.
    Chaves R, Sousa L (2003) RDSP: a RISC DSP based on residue number system. In: Proceedings of 6th Euromicro symposium on digital system design, pp 128–135. doi: 10.1109/dsd.2003.1231911
  4. 4.
    Fernandez PG, Lloris A (2003) RNS-based implementation of 8x8 point 2D-DCT over field-programmable devices. Electron Lett 39:21–23. doi: 10.1049/el:20030084 CrossRefGoogle Scholar
  5. 5.
    Liu Y, Lai E (2004) Moduli set selection and cost estimation for RNS-based FIR filter and filter bank design. Des Autom Embed Syst 9:123–139. doi: 10.1007/s10617-005-1186-4 CrossRefGoogle Scholar
  6. 6.
    Cardarilli G, Nannarelli A, Re M (2007) Residue number system for low-power DSP applications. In: Proceedings of asilomar conference on signals, systems and computers, pp 1412–1416. doi: 10.1109/acssc.2007.4487461
  7. 7.
    Bajard JC, Imbert L (2004) A full RNS implementation of RSA. IEEE Trans Comput 53:769–774. doi: 10.1109/tc.2004.2 CrossRefGoogle Scholar
  8. 8.
    Meyer-Baese U, Garcia A, Taylor F (2001) Implementation of a communications channelizer using FPGAs and RNS arithmetic. J VLSI Signal Process 28:115–128. doi: 10.1023/a:1008167323437 zbMATHCrossRefGoogle Scholar
  9. 9.
    Madhukumar AS, Chin F (2004) Enhanced architecture for residue number system-based CDMA for high-rate data transmission. IEEE Trans Wireless Commun 3:1363–1368. doi: 10.1109/twc.2004.833509 CrossRefGoogle Scholar
  10. 10.
    Avizienis A (1961) Signed-digit representation for fast parallel arithmetic. IRE Trans Electron Comput EC-10:389–400. doi: 10.1109/tec.1961.5219227 MathSciNetCrossRefGoogle Scholar
  11. 11.
    Jaberipur G, Parhami B, Ghodsi M (2005) Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. IEEE Trans Circuits Syst I 52:1348–1357. doi: 10.1109/tcsi2005.851679 MathSciNetCrossRefGoogle Scholar
  12. 12.
    Jaberipur G, Parhami B (2007) Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic. IET Circuits Devices Syst 1:102–110. doi: 10.1049/iet-cds:20050228 CrossRefGoogle Scholar
  13. 13.
    Jaberipur G, Parhami B (2009) Unified approach to the design of modulo-(2n ± 1) adders based on signed-LSB representation of residues. In: Proceedings of IEEE international symposium on computer arithmetic, pp 57–64. doi: 10.1109/arith.2009.14
  14. 14.
    Lindstrom A, Nordseth M, Bengtsson L, Omondi A (2003) Arithmetic circuits combining residue and signed-digit representations. In: Proceedings of 8th Asia-Pacific computer systems architecture conference, pp 246–257. doi: 10.1007/978-3-540-39864-6_20
  15. 15.
    Wei S (2008) A new residue adder with redundant binary number representation. In: Proceedings of 6th international IEEE north-east workshop on circuits and systems, pp 157–160. doi: 10.1109/newcas.2008.4606345
  16. 16.
    Persson A, Bengtsson L (2009) Forward and reverse converters and moduli set selection in signed-digit residue number systems. J Signal Process Syst 56:1–15. doi: 10.1007/s11265-008-0249-8 CrossRefGoogle Scholar
  17. 17.
    Timarchi S, Navi K (2007) Efficient class of redundant residue number system. In: Proceedings of IEEE international symposium on intelligent signal processing, pp 475–780. doi: 10.1109/wisp.2007.4447506
  18. 18.
    Timarchi S, Navi K (2009) Arithmetic circuits of redundant SUT-RNS. IEEE Trans Instrum Meas 58:2959–2968. doi: 10.1109/tim.2009.2016793 CrossRefGoogle Scholar
  19. 19.
    Kogge PM, Stone HS (1973) A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans Comput 22:786–792. doi: 10.1109/tc.1973.5009159 MathSciNetzbMATHCrossRefGoogle Scholar
  20. 20.
    Vergos HT, Bakalis D, Efstathiou C (2010) Fast modulo 2n + 1 multi-operand adders and residue generators. Integr VLSI J 43:42–48. doi: 10.1016/j.vlsi.2009.04.002 CrossRefGoogle Scholar
  21. 21.
    Tyagi A (1993) A reduced-area scheme for carry-select adders. IEEE Trans Comput 42:1163–1170. doi: 10.1109/12.257703 CrossRefGoogle Scholar
  22. 22.
    Kalampoukas L, Nikolos D, Efstathiou C, Vergos HT, Kalamatianos J (2000) High-speed parallel prefix modulo 2n–1 adders. IEEE Trans Comput 49:673–680. doi: 10.1109/12.863036 CrossRefGoogle Scholar
  23. 23.
    Vergos HT, Efstathiou C, Nikolos D (2002) Diminished-one modulo 2n + 1 adder design. IEEE Trans Comput 51:1389–1399. doi: 10.1109/tc.2002.1146705 MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Electronics Laboratory, Department of PhysicsUniversity of PatrasPatrasGreece
  2. 2.Department of Computer Engineering and InformaticsUniversity of PatrasPatrasGreece

Personalised recommendations