Reducing the Computational Complexity of Look-Ahead DD Conversion

  • Erwin Janssen
  • Arthur van Roermund
Part of the Analog Circuits and Signal Processing book series (ACSP)


In this chapter the possibilities for reducing the computational load of look-ahead digital-to-digital conversion are explored. An analysis is made of the opportunities to reduce the number of computations required to perform full look-ahead. For small look-ahead depth it is possible to reduce the number of calculations, but for large look-ahead depths the savings that can be realized are limited, and ultimately the number of computations that are required per output symbol doubles with an increase of the look-ahead depth by one. As an alternative to full look-ahead, the possibilities for performing pruned look-ahead are explored. In this case not the full solution space is explored, but based on heuristics a small subset of all the solutions are investigated. This approach can realize a large reduction of the computational load, while the impact on the signal conversion performance can be made negligible small. Because of the potentially large advantage over full look-ahead, several ideas for realizing pruned look-ahead modulators are presented, that are explored in detail in the next chapters.


Input Signal Impulse Response Clock Cycle Filter Output Loop Filter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Mixed Signal Circuits & SystemsNXP Semiconductors, Central R&DEindhovenThe Netherlands
  2. 2.Electrical Engineering, Mixed-signal Microelectronics GroupTechnical University EindhovenEindhovenThe Netherlands

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