Abstract
Recent integration of functional materials in a microelectronic architecture led to new memory concepts presenting disruptive performances as compared to conventional technologies. Beside solutions based on charge storage in a floating gate (EEPROM, Flash, etc.), these alternative devices involve voltage or current-controlled switching mechanisms between two distinct resistance states. The origin of the resistance switching straightforwardly depends upon the nature and fundamental physical properties of functional materials integrated in the memory cell. After a general overview of nonvolatile memories, this chapter will focus on the materials integrated in these emerging concepts and on their ability to withstand a downscaling of their critical dimensions. In addition, considering the novelty of these technologies, a peculiar attention will be turned towards the models describing memory cell operations and their implementation in electrical simulators to evaluate robustness of innovative architectures.
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Van Houdt, Y., Wouters, D.J.: Memory technology: where is it going? Semicond. Int. 29(13), 58–62 (2006)
Scott, J.F.: Ferroelectric Memories. Springer, Berlin (2000)
Böttger, U., Summerfelt, S.R.: In: Waser, R. (ed.) Nanoelectronics and Information Technology. Wiley-VCH, Weinheim (2003)
Nagai, A., et al.: Conformality of Pb(Zr,Ti)O3 films deposited on trench structures having submicrometer diameter and various aspect ratios. Electrochem. Solid-State Lett. 9(1), C15–C18 (2006)
Goux, L., Russo, G., Menou, N., Lisoni, J.G., Schwitters, M., Paraschiv, V., Maes, D., Artoni, C., Corallo, G., Haspeslagh, L., Wouters, D.J., Zambrano, R., Muller, Ch.: A highly reliable 3-dimensional integrated SBT ferroelectric capacitor enabling FeRAM scaling. IEEE Trans. Electron Devices 52(4), 447–453 (2005)
Menou, N., Turquat, Ch., Madigou, V., Muller, Ch., Goux, L., Lisoni, J.G., Schwitters, M., Wouters, D.J.: Sidewalls contribution in integrated three-dimensional Sr0.8Bi2.2Ta2O9-based ferroelectric capacitors. Appl. Phys. Lett. 87(7), 073502 (2005)
Tehrani, S.: Status and outlook of MRAM memory technology. In: IEEE Proc. of Int. Electron Device Meeting, pp. 1–4 (2006)
Engel, B.N., et al.: A 4-Mbit Toggle MRAM based on a novel bit and switching method. IEEE Trans. Magn. 41, 132–136 (2005)
Andre, T.W., Nahas, J.J., Subramanian, C.K., Garni, B.J., Lin, H.S., Omair, A., Martino, W.L.: A 4 Mb 0.18 μm 1T1MTJ Toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers. IEEE J. Solid-State Circuits 40(1), 301–309 (2005)
Savtchenko, L., et al.: Method of writing to scalable magnetoresistive random access memory element. US Patent 6,545,906 B1, 8 April 2003
Naji, P.K., DeHerrera, M., Durlam, M.: MTJ MRAM series-parallel architecture, US Patent 6,331,943 B1, 18 December 2001
Mattson, J.: Magnetoresistive memory devices, US Patent 6,806,523 B2, 19 October 2004
Leung, E.T.: Enhanced MRAM reference bit programming structure, US Patent 7,411,816 B2, 12 August 2008
Nahas, J.J., Andre, T.W., Garni, B., Subramanian, C., Lin, H., Alam, S.M., Papworth, K., Martino, W.L.: A 180 Kbit embeddable MRAM memory module. IEEE J. Solid-State Circuits 43, 1826–1834 (2008)
Slaughter, J.M.: Recent advances in MRAM technology. In: IEEE Proc. of Device Research Conference, pp. 245–246 (2007)
Prejbeanu, I.L., Kula, W., Ounadjela, K., Sousa, R.C., Redon, O., Dieny, B., Nozières, J.P.: Thermally assisted switching in exchange-biased storage layer magnetic tunnel junctions. IEEE Trans. Magn. 40(4), 2625–2627 (2004)
Sousa, R.C., Kerekes, M., Prejbeanu, I.L., Redon, O., Dieny, B., Nozières, J.P., Freitas, P.P.: Crossover in heating regimes of thermally assisted magnetic memories. J. Appl. Phys. 99(8), 08N904 (2006)
Cardoso, S., Ferreira, R., Silva, F., Freitas, P.P., Melo, L.V., Sousa, R.C., Redon, O., MacKenzie, M., Chapman, J.N.: Double-barrier magnetic tunnel junctions with GeSbTe thermal barriers for improved thermally assisted magnetoresistive random access memory cells. J. Appl. Phys. 99(8), 08N901 (2006)
TIMI, Thermally Insulating MRAM Interconnects, EURIPIDES project no. EUR-06-204; Partners: Crocus Technology (leader), Singulus, Tower Semiconductor, and IM2NP
Nagai, H., Huai, Y., Ueno, S., Koga, T.: Spin-transfer torque writing technology (STT-RAM) for future MRAM. IEIC Tech. Rep. 106(2), 73–78 (2006)
Diao, Z., et al.: Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory. J. Phys., Condens. Matter 19(16), 165209–165221 (2007)
Prenat, G., El Baraji, M., Wei, G., Sousa, R., Buda-Prejbeanu, L., Dieny, B., Javerliac, V., Nozières, J.-P., Zhao, W., Belhaire, E.: CMOS/magnetic hybrid architectures. In: IEEE Proc. of Int. Conf. on Electronics, Circuits and Systems, pp. 190–193 (2007)
CILOMAG, Circuits Logiques Magnétiques, ANR project no. ANR-06-NANO-066; Partners: IEF (leader), Spintec, Crocus, CEA-LETI, CMP, and LIRMM
Das, B., Black, W.C.: A generalized HSPICE macro-model for pinned spin-dependent-tunneling devices. IEEE Trans. Magn. 35(5), 2889–2891 (1999)
Kammerer, J.B., Hebrard, L., Hehn, M., Braun, F., Alnot, P., Schuhl, A.: Compact modeling of a magnetic tunnel junction using VHDL-AMS: computer aided design of a two-axis magnetometer. In: Proceedings of IEEE Sensors 2004, vol. 3, pp. 1558–1561 (2004)
Madec, M., Kammerer, J.B., Pregaldiny, F., Hebrard, L., Lallement, C.: Compact modeling of magnetic tunnel junction. In: IEEE Proc. of Northeast Workshop on Circuits and Systems and TAISA Conf., pp. 229–232 (2008)
Hass, K.J.: Radiation-tolerant embedded memory using magnetic tunnel junctions. Ph.D. Thesis, University of Idaho (2007)
Russo, U., Ielmini, D., Cagli, C., Lacaita, A.L.: Filament conduction and reset mechanism in NiO-based resistive-switching memory (RRAM) devices. IEEE Trans. Electron Devices 56(2), 186–192 (2009)
Russo, U., Ielmini, D., Cagli, C., Lacaita, A.: Self-accelerated thermal dissolution model for reset programming in unipolar resistive-switching memory (RRAM) devices. IEEE Trans. Electron Devices 56(2), 193–199 (2009)
Hosomi, M., et al.: A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM. In: IEEE Proc. of Int. Electron Device Meeting, pp. 459–462 (2005)
Gogl, D., et al.: A 16-Mb MRAM featuring bootstrapped write drivers. IEEE J. Solid-State Circuits 40(4), 902–908 (2005)
Nicolle, E.: Caractérisations et fiabilité de mémoires magnétiques à accès aléatoires (MRAM). Ph.D. Thesis, Université Paris Sud (2008)
Durlam, M., et al.: 90 nm toggle MRAM array with 0.29 μm2 cells. In: IEEE Proc. of VLSI Technology Symp., pp. 186–187 (2005)
Liaw, J.-J., Tang, D.: High speed sensing amplifier for an MRAM cell. US Patent 7,286,429 B1, 23 October 2007
Bruchon, N., Torres, L., Sassatelli, G., Cambon, G.: Magnetic tunnelling junction based FPGA. In: Proc of Int. Symp. on Field Programmable Gate Arrays, pp. 123–130 (2006)
Guillemenet, Y., Torres, L., Sassatelli, G., Bruchon, N.: On the use of magnetic RAMs in field-programmable gate arrays. Int. J. Reconfigurable Comput. 2008, 1–9 (2008)
Cho, W.-Y., et al.: A 0.18 μm 3.0 V 64 Mb nonvolatile Phase transition Random Access Memory (PRAM). IEEE J. Solid-State Circuits 40(1), 293–300 (2005)
Cho, B.-H., Cho, W.-Y., Park, M.-H.: Phase change memory device generating program current and method thereof. US Patent 7,656,719 B2, 2 February 2010
Oh, J.H., et al.: Full integration of highly manufacturable 512 Mb PRAM based on 90 nm technology. In: IEEE Proc. of Int. Electron Device Meeting, pp. 49–52 (2006)
Kang, S., et al.: A 0.1-μm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) with 66 MHz synchronous burst-read operation. IEEE J. Solid-State Circuits 42(1), 210–218 (2007)
Ovshinsky, S.R.: Reversible electrical switching phenomenon in disordered structures. Phys. Rev. Lett. 21(20), 1450–1453 (1968)
Lankhorst, M.H.R., Ketelaars, B.W., Wolters, R.A.: Low-cost and nanoscale non-volatile memory concept for future silicon chips. Nat. Mater. 4(4), 347–352 (2005)
Castro, D.T., Goux, L., Hurkx, G.A.M., Attenborough, K., Delhougne, R., Lisoni, J., Jedema, F.J., Wolters, R.A.M., Gravesteijn, D.J., Verheijen, M.A., Kaiser, M., Weemaes, R.G.R., Wouters, D.J.: Evidence of the thermo-electric Thomson effect and influence on the program conditions and cell optimization in phase-change memory cells. In: IEEE Proc. of Int. Electron Device Meeting, pp. 315–318 (2007)
Chen, Y.C., et al.: Ultra-thin phase change bridge memory device using GeSb. In: IEEE Proc. of Int. Electron Device Meeting, pp. 777–780 (2006)
Raoux, S., et al.: Phase-change random access memory: a scalable technology. IBM J. Res. Dev. 52(4/5), 465–479 (2008)
Hush, G., Baker, J.: Complementary bit PCRAM sense amplifier and method of operation, US Patent 6,791,859 B2, 14 September 2004
Chen, S.-H., Lung, H.-L.: Thin film plate phase change RAM circuit and manufacturing method, US Patent 7,238,994 B2, 3 July 2007
Adler, D., Shur, M.S., Silver, M., Ovshinsky, S.R.: Threshold switching in chalcogenide-glass thin films. J. Appl. Phys. 51(6), 3289–3309 (1980)
Radaelli, A., Pirovano, A., Benvenuti, A., Lacaita, A.: Threshold switching and phase transition numerical models for phase change memory simulations. J. Appl. Phys. 103(11), 111101 (2008)
Ielmini, D., Zhang, Y.: Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices. J. Appl. Phys. 102(5), 054517 (2007)
Karpov, I.V., Mitra, M., Kau, D., Spadini, G., Kryukov, Y.A., Karpov, V.G.: Fundamental drift of parameters in chalcogenide phase change memory. J. Appl. Phys. 102(12), 124503 (2007)
Lee, B.C., Ipek, E., Mutlu, O., Burger, D.: Architecting phase change memory as a scalable dram alternative. Comput. Archit. News 37(3), 2–13 (2009)
Gill, M., Lowrey, T., Park, J.: Ovonic unified memory—a high-performance nonvolatile memory technology for stand-alone memory and embedded applications. In: IEEE Proc. Int. Solid State Circuits Conf., vol. 1, pp. 202–204 (2002)
Hyung-rok, O., et al.: Enhanced write performance of a 64 Mb phase-change random access memory. IEEE J. Solid-State Circuits 41(1), 122–126 (2006)
Bedeschi, F., Resta, C., Khouri, O., Buda, E., Costa, L., Ferraro, M., Pellizzer, F., Ottogalli, F., Pirovano, A., Tosi, M., Bez, R., Gastaldi, R., Casagrande, G.: An 8 Mb demonstrator for high-density 1.8 V phase-change memories. In: IEEE Proc. of VLSI Circuits Symp., pp. 442–445 (2004)
Hsu, S.T., Pan, W., Zhang, F., Zhuang, W.-W., Li, T.: RRAM memory cell electrodes, US Patent 6,849,891 B1, 1 February 2005
Lee, C.-B., Park, Y.-S., Lee, M.-J., Wenxu, X., Kang, B.-S., Ahn, S.-E., Kim, K.-H.: Resistive memory devices and methods of manufacturing the same, US Patent 2009/0184305 A1, 23 July 2009
Malhotra, S.G., Kumar, P., Barstow, S., Chiang, T., Phatak, P.B., Wu, W., Shanker, S.: Nonvolatile memory elements, US Patent 2009/0026434 A1, 29 January 2009
Waser, R., Aono, M.: Nanoionics-based resistive switching memories. Nature 6, 833–840 (2007)
ITRS, International Technology Roadmap for Semiconductors: Emerging Research Devices; Process Integration, Devices and Structures. http://www.itrs.net/ (2009)
Sawa, A.: Resistive switching in transition metal oxides. Mater. Today 11(6), 28–36 (2008)
Courtade, L., Lisoni-Reyes, J., Goux, L., Turquat, C., Muller, Ch., Wouters, D.J.: Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof. US Patent 7,960,775 B2, 14 June 2011
Courtade, L., Turquat, Ch., Muller, Ch., Lisoni, J.G., Goux, L., Wouters, D.J., Goguenheim, D., Roussel, P., Ortega, L.: Oxidation kinetics of Ni metallic film: formation of NiO-based resistive switching structures. Thin Solid Films 516(12), 4083–4092 (2008)
Courtade, L., Turquat, Ch., Lisoni, J.G., Goux, L., Wouters, D.J., Deleruyelle, D., Muller, Ch.: Integration of resistive switching NiO in small via structures from localized oxidation of nickel metallic layer. In: IEEE Proc. of European Solid State Device Research Conf., pp. 218–221 (2008)
Spiga, S., Lamperti, A., Wiemer, C., Perego, M., Cianci, E., Tallarida, G., Lu, H.L., Alia, M., Volpe, F.G., Fanciulli, M.: Resistance switching in amorphous and crystalline binary oxides grown by electron beam evaporation and atomic layer deposition. Microelectron. Eng. 85(12), 2414–2419 (2008)
Dumas, C., Deleruyelle, D., Demolliens, A., Muller, Ch., Spiga, S., Cianci, E., Fanciulli, M., Tortorelli, I., Bez, R.: Resistive switching characteristics of NiO films deposited on top of W and Cu pillar bottom electrodes. Thin Solid Films 519(11), 3798–3803 (2011)
Symanczyk, R., Dittrich, R., Keller, J., Kund, M., Muller, G., Ruf, B., Albarede, P.-H., Bournat, S., Bouteille, L., Duch, A.: Conductive bridging memory development from single cells to 2 Mbit memory arrays. In: IEEE Proc. of Nonvolatile Memory Technology Symp., pp. 71–75 (2007)
Bocquet, M., Deleruyelle, D., Muller, Ch., Portal, J.-M.: Self-consistent physical modelling of set/reset operations in unipolar resistive-switching memories. Appl. Phys. Lett. 98(26), 263507 (2011)
Kozicki, M.N., Park, M., Mitkova, M.: Nanoscale memory elements based on solid-sate electrolytes. IEEE Trans. Nanotechnol. 4(3), 331–338 (2005)
Strukov, D.B., et al.: The missing memristor found. Nature 453, 80–83 (2008)
Meyer, R., Schloss, L., Brewer, J., Lambertson, R., Kinney, W., Sanchez, J., Rinerson, D.: Oxide dual-layer memory element for scalable non-volatile cross-point memory technology. In: IEEE Proc. of Nonvolatile Memory Technology Symp., pp. 54–58 (2008)
Deleruyelle, D., Muller, Ch., Amouroux, J., Müller, R., Electrical nano-characterization of copper tetracyanoquinodimethane layers dedicated to resistive random access memories. Appl. Phys. Lett. 96(26), 263504 (2011)
Chae, S.C., et al.: Random circuit breaker network model for unipolar resistance switching. Adv. Mater. 20, 1154–1159 (2008)
Liu, C., et al.: Abnormal resistance switching behaviours of NiO thin films: possible occurrence of both formation and rupturing of conducting channels. J. Phys. D, Appl. Phys. 42(1), 015506 (2009)
EMMA, Emerging Materials for Mass-storage Architectures: IST project no. 33751. Partners: IMEC, Numonyx, MDM, IUNET, RWTH-Aachen, and IM2NP, http://www.imec.be/EMMA
Cagli, C., Ielmini, D., Nardi, F., Lacaita, A.L.: Evidence for threshold switching in the set process of NiO-based RRAM and physical modeling for set, reset, retention and disturb prediction. In: IEEE Proc. of Int. Electron Device Meeting, pp. 301–304 (2008)
Ginez, O., Portal, J.-M., Muller, Ch.: Design and test challenges in resistive switching RAM (ReRAM): an electrical model for defect injections. In: IEEE Proc. of European Test Symp., pp. 61–66 (2009)
Lee, M.-J., et al.: 2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications. In: IEEE Proc. of Int. Electron Device Meeting, pp. 771–774 (2007)
Hosoi, Y., et al.: High speed unipolar switching resistance RAM (RRAM) technology. In: IEEE Proc. of Int. Electron Device Meeting, pp. 1–4 (2006)
Kinoshita, K., et al.: Reduction in the reset current in a resistive random access memory consisting of NiO x brought about by reducing a parasitic capacitance. Appl. Phys. Lett. 93(3), 033506 (2008)
Dietrich, S., et al.: A nonvolatile 2-Mbit CBRAM memory core featuring advanced read and program control. IEEE J. Solid-State Circuits 42(4), 839–845 (2007)
Kund, M., et al.: Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20 nm. In: IEEE Proc. of Int. Electron Device Meeting, pp. 754–757 (2005)
Liaw, C., Symanczyk, R.: A Method for operating a PMC memory and CBRAM memory circuit, European Patent 1727151 B1, 27 February 2008
Hoenigschmid, H., et al.: Resistive memory device and method for writing to a resistive memory cell in a resistive memory device, US Patent 7,518,902 B2, 14 April 2009
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Muller, C., Deleruyelle, D., Ginez, O. (2012). Emerging Memory Concepts. In: Nicolescu, G., O'Connor, I., Piguet, C. (eds) Design Technology for Heterogeneous Embedded Systems. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1125-9_16
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