Logic Design with Ambipolar Devices

  • M. Haykel Ben Jamaa
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 82)


In this part of the book, the work is based on a different technology from the previous chapters. Carbon nanotubes are another candidate for the extension of CMOS by replacing the silicon channel. The CNT technology also promises novel ways to design logic circuits by leveraging its ability to on-line control the device polarity. Despite the expected large performance enhancement, there are still many issues related to this immature technology to be resolved.


Logic Gate Dynamic Logic Logic Family Device Polarity Polarity Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Kang SJ et al (2007) High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. Nat Nanotechnol 2(4):230–236CrossRefGoogle Scholar
  2. 2.
    Zhang G, Qi P, Wang X, Lu Y, Li X, Tu R, Bangsaruntip S, Mann D, Zhang L, Dai H (2006) Selective etching of metallic carbon nanotubes by gas-phase reaction. Science 314(5801):974–977CrossRefGoogle Scholar
  3. 3.
    Zhang J, Patil N, Mitra S (2008) Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits. In: Proceedings of DATE, pp 1009–1014Google Scholar
  4. 4.
    Patil N, Deng J, Lin A, Wong H-SP, Mitra S (2008) Design methods for misaligned and mispositioned carbon-nanotube-immune circuits. IEEE Trans Computer-Aided Des Integr Circuits Syst 27(10):1725–1736CrossRefGoogle Scholar
  5. 5.
    Patil JZ et al (2009) Carbon nanotube circuits in the presence of carbon nanotube density variations. July 2009Google Scholar
  6. 6.
    Lin YM, Appenzeller J, Avouris P (2004) Novel carbon nanotube FET design with tunable polarity. In: IEEE International Electron Devices Meeting 2004. IEDM Technical Digest, pp 687–690Google Scholar
  7. 7.
    Lin Y-M, Appenzeller J, Knoch J, Avouris P (2005) High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans Nanotechnol 4(5):481–489CrossRefGoogle Scholar
  8. 8.
    O’Connor I, Junchen L, Gaffiot F, Pregaldiny F, Lallement C, Maneux C, Goguet J, Fregonese S, Zimmer T, Anghel L, Dang T-T, Leveugle R (2007) CNTFET modeling and reconfigurable logic-circuit design. IEEE Trans Circuits Syst I: Regul Pap 54(11):2365–2379CrossRefGoogle Scholar
  9. 9.
    O’Connor I, Liu J, Gaffiot F (2006) CNTFET-based logic circuit design. In: Proceedings of the International Conference Design and Test of Integrated Systems (DTIS), pp 46–51Google Scholar
  10. 10.
    Ben-Jamaa MH, Atienza D, Leblebici Y, Micheli GD (2008) Programmable logic circuits based on ambipolar CNFET. In: Proceedings of the Design Automation Conference (DAC), pp 339–340Google Scholar
  11. 11.
    Ben Jamaa MH, Mohanram K, De Micheli G (2009) Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis. In: Proceedings of DATEGoogle Scholar
  12. 12.
    Dresselhaus M, Dresselhaus G, Avouris P (2001) Carbon nanotubes: synthesis, structure properties and applications. Springer, HeidelbergCrossRefGoogle Scholar
  13. 13.
    Derycke V, Martel R, Appenzeller J, Avouris P (2001) Carbon nanotube inter- and intramolecular logic gates. Nano Lett 1(9):453–456CrossRefGoogle Scholar
  14. 14.
    Yang Q, Xiao C, Chen W, Singh AK, Asai T, Hirose A (2003) Growth mechanism and orientation control of well-aligned carbon nanotubes. Diam Relat Mater 12(9):1482–1487CrossRefGoogle Scholar
  15. 15.
    Patil N, Lin A, Myers E, Wong HS, Mitra S (2008) Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures. In: 2008 Symposium of the VLSI Technology, pp 205–206Google Scholar
  16. 16.
    Patil N, Deng J, Wong H-SP, Mitra S (2007) Automated design of misaligned-carbon-nanotube-immune circuits. In: DAC ’07: Proceedings of the 44th annual conference on Design automation, pp 958–961Google Scholar
  17. 17.
    Deng J, Patil N, Ryu K, Badmaev A, Zhou C, Mitra S, Wong H-SP (2007) Carbon nanotube transistor circuits: circuit-level performance benchmarking and design options for living with imperfections. In: IEEE ISSCC Tech. Dig., pp 70–588Google Scholar
  18. 18.
    Bachtold A, Hadley P, Nakanishi T, Dekker C (2001) Logic circuits with carbon nanotube transistors. Science 294:1317–1320CrossRefGoogle Scholar
  19. 19.
    Choudhury M, Yoon Y, Guo J, Mohanram K (2008) Technology exploration for graphene nanoribbon FETs. In: Proceedings of the Design Automation Conference (DAC), pp 272–277Google Scholar
  20. 20.
    Liu J, O’Connor I, Navarro D, Gaffiot F (2007) Novel CNTFET-based reconfigurable logic gate design. In: Annual ACM IEEE Design Automation Conference, pp 276–277Google Scholar
  21. 21.
    Heinze S, Tersoff J, Martel R, Derycke V, Appenzeller J, Avouris P (2002) Carbon nanotubes as Schottky barrier transistors. Phys Rev Lett 89(10):106801CrossRefGoogle Scholar
  22. 22.
    Guo J, Datta S, Lundstrom M (2004) A numerical study of scaling issues for Schottky-barrier carbon nanotube transistors. IEEE Trans Electron Devices 51(2):172–177CrossRefGoogle Scholar
  23. 23.
    Close GF, Yasuda S, Paul B, Fujita S, Wong H-SP (2008) A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors. Nano Lett 8(2):706–709CrossRefGoogle Scholar
  24. 24.
    Javey A, Guo J, Farmer DB, Wang Q, Yenilmez E, Gordon RG, Lundstrom M, Dai H (2004) Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays. Nano Lett 4(7):1319–1322CrossRefGoogle Scholar
  25. 25.
    Stanford University CNFET model (2008)Google Scholar
  26. 26.
    Goncalves NF, De Man H (1983) NORA: a racefree dynamic CMOS technique for pipelined logic structures. IEEE J Solid-State Circuits 18(3):261–266CrossRefGoogle Scholar
  27. 27.
    Weste NHE, Harris D (2005) CMOS VLSI design: a circuits and systems perspective. Pearson/Addison Wesley, BostonGoogle Scholar
  28. 28.
    ABC logic synthesis tool. Available at for further details
  29. 29.
    Kheterpal V et al (2005) Design methodology for IC manufacturability based on regular logic-bricks. In: Design Automation Conference, pp 353–358Google Scholar
  30. 30.
    Mo F, Brayton RK (2002) Whirlpool PLAs: a regular logic structure and their synthesis. In: International Conference on Computer-Aided Design, pp 543–550Google Scholar
  31. 31.
    Ran Y, Marek-Sadowska M (2006) Designing via-configurable logic blocks for regular fabric. Trans Very Large Scale Integr (VLSI) Syst 14(1):1–14CrossRefGoogle Scholar
  32. 32.
    Brockman J, Li S, Kogge P, Kashyap A, Mojarradi M (2008) Design of a mask-programmable memory/multiplier array using G4-FET technology. In: Proceedings of the Design Automation Conference (DAC), pp 337–338Google Scholar
  33. 33.
    Brown J, Taylor B, Blanton R, Pileggi L (2008) Automated testability enhancements for logic brick libraries. In: DATE 2008, pp 480–485Google Scholar
  34. 34.
    Yang S (2001) Logic synthesis and optimization benchmarks user guide version 3.0. Microelectronics Center of North Carolina, Tech. Rep., 2001Google Scholar
  35. 35.
    Sasao T (1984) Input variable assignment and output phase optimization of PLA’s. IEEE Trans Comput 33(10):879–894MathSciNetzbMATHCrossRefGoogle Scholar
  36. 36.
    Brayton, RK Mo F (2002) Whirlpool PLAs: a regular logic structure and their synthesis. In: International Conference on Computer-Aided Design, pp 543–550Google Scholar
  37. 37.
    Schmid Y, Leblebici A (2004) Fault-tolerant PLA-style circuit design for failure-prone nanometer CMOS and quantum device technologies. In: Proceedings of the 2004 IEEE International Joint Conference on Neural Networks, 2004, vol 3, pp 1965–1969, 25–29 July 2004Google Scholar
  38. 38.
    Sasao T (1993) EXMIN2: A simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions. IEEE Trans Computer-Aided Des 12(5):621–632CrossRefGoogle Scholar
  39. 39.

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Commissariat à l’Energie Atomique (CEA-L DRT-LETI-DACLE-LISAN)GrenobleFrance

Personalised recommendations