A SystemC Platform for NoC Analysis
  • Stefano Gigli
  • Massimo Conti
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 81)


Communication architecture is a crucial part of the design for performances and power constraints in modern multicore systems on chip. A SystemC class library and relative tools for comparing different Network-on-Chip (NoC) architectures and investigating communication bottlenecks is presented in this chapter. NoCs are compared by statistical analysis of packet delays and power dissipation is evaluated on NoC component activities; probabilistic investigations, temporal evolutions and a packet tracing tool allow to discover, identify and localize bottlenecks.


Clock Cycle Traffic Intensity Output Port Communication Architecture Traffic Scenario 
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  1. 1.
    de Micheli G, Benini L (2002) Networks on chip: a new paradigm for systems on chip design. In: DATE ‘02: Proceedings of the conference on design, automation and test in Europe. IEEE Computer Society, Washington, p 418Google Scholar
  2. 2.
    Kornaros G (2010) Multi-core embedded systems. Taylor & Francis, Boca RatonCrossRefGoogle Scholar
  3. 3.
    Bononi L, Concer N (2006) Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. In: Proceedings of design, automation and test in Europe (DATE), MarchGoogle Scholar
  4. 4.
    Dolter JW, Ramanathan P, Shin KG (1991) Performance analysis of virtual cut-through switching in HARTS: a hexagonal mesh multicomputer. IEEE Trans Multicomput 40(6):669–680MathSciNetGoogle Scholar
  5. 5.
    Zhao Y-J, Yue Z-H, Wu JP (2008) Research on next-generation scalable routers implemented with H-torus topology. J Comput Sci Technol 23(4):684MathSciNetCrossRefGoogle Scholar
  6. 6.
    Guerrier P, Greiner A (2000) A generic architecture for on-chip packet switched interconnections. In: Proceedings of DATE. ACM Press, pp 250–256Google Scholar
  7. 7.
    Kariniemi H, Nurmi J (2003) New adaptive routing algorithm for extended generalized fat trees on-chip. In: Proceedings of the international symposium on system-on-chip, Tampere, Finland, pp 113–188Google Scholar
  8. 8.
    Ohring SR, Ibel M, Das SK, Kumar M (1995) On generalized fat trees. In: Proceedings on 9th international parallel processing symposiumGoogle Scholar
  9. 9.
    Moussa H, Muller O, Baghdadi A, Jezequel M (2007) Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. In: Design automation and test in Europe conferenceGoogle Scholar
  10. 10.
    Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) QNoC: QoS architecture and design process for network on chip. J Syst Arch Spec Issue Netw Chip 50:105–128CrossRefGoogle Scholar
  11. 11.
    Soteriou V, Peh L-S (2004) Design-space exploration for power-aware on/off interconnection networks. In: Proceedings of the 22nd international conference on computer design (ICCD)Google Scholar
  12. 12.
    Shang L, Peh L-S, Jha NK (2002) Power-efficient interconnection networks: dynamic voltage scaling with links. Comput Arch Lett 1(2):1–4Google Scholar
  13. 13.
    Bhat S (2005) Energy models for network on chip components. Ph.D. dissertation, Technische universiteit EindhovenGoogle Scholar
  14. 14.
    Laffely A, Liang J, Jain P, Weng N, Burleson W, Tessier R (2001) Adaptive system on a chip (aSoC) for lowpower signal processing. In: Thirty-fifth asilomar conference on signals, systems, and computers, NovemberGoogle Scholar
  15. 15.
    Liang J, Swaminathan S, Tessier R (2000) aSOC: a scalable, single-chip communications architecture. In: IEEE international conference on parallel architectures and compilation techniques, October, pp 524–529Google Scholar
  16. 16.
    Dally WJ (1990) Virtual-channel flow control. In: Proceedings of the 17th annual international symposium on computer architecture (ISCA), Seattle, Washington, May, pp 60–68Google Scholar
  17. 17.
    Kermani P, Kleinrock L (1979) Virtual cut-through: a new computer communication switching technique. Comput Netw 3:267–286MathSciNetzbMATHGoogle Scholar
  18. 18.
    Dally WJ, Seitz CL (1986) The torus routing chip. J Parallel Distrib Comput 1(3):187–196Google Scholar
  19. 19.
    Peh L-S, Dally WJ (2000) Flit-reservation flow control. In: Proceedings of the 6th international symposium on high-performance computer architecture (HPCA), January, pp 73–84Google Scholar
  20. 20.
    Dally W, Seitz C (1987) Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans Comput C-36(5):547–553CrossRefGoogle Scholar
  21. 21.
    Glass C, Ni L (1994) The turn model for adaptive routing. J ACM 5:874–902CrossRefGoogle Scholar
  22. 22.
    Duato J (1995) A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Process 6(10):1055–1067CrossRefGoogle Scholar
  23. 23.
    Duato J (1996) A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks. IEEE Trans Parallel Distrib Process 7:841–854CrossRefGoogle Scholar
  24. 24.
    Gigli S, Conti M (2009) A SystemC platform for Network-on-Chip performance/power evaluation and comparison. In: Proceedings of the IEEE seventh international workshop on intelligent solutions in embedded systems WISES09, pp 63–69, Ancona, Italy, June 25–26Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.DIBETUniversita Politecnica delle MarcheAnconaItaly

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