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NOCEXplore

A SystemC Platform for NoC Analysis
  • Stefano Gigli
  • Massimo Conti
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 81)

Abstract

Communication architecture is a crucial part of the design for performances and power constraints in modern multicore systems on chip. A SystemC class library and relative tools for comparing different Network-on-Chip (NoC) architectures and investigating communication bottlenecks is presented in this chapter. NoCs are compared by statistical analysis of packet delays and power dissipation is evaluated on NoC component activities; probabilistic investigations, temporal evolutions and a packet tracing tool allow to discover, identify and localize bottlenecks.

Keywords

Clock Cycle Traffic Intensity Output Port Communication Architecture Traffic Scenario 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.DIBETUniversita Politecnica delle MarcheAnconaItaly

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