Skip to main content

Cost-Based Deflection Routing for Intelligent NoC Switches

  • Chapter
  • First Online:
  • 1213 Accesses

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 81))

Abstract

Future manycore systems-on-chip will employ packet-switched, multi-hop interconnection networks-on-chip (NoC). In order to cope with disturbances from, e.g., faults or local traffic overload, some degree of intelligence and adaptivity has to be built into NoC switches. They need to know about their own and their environment’s fault and traffic status and take this information into account when making routing decisions. We present an approach that selects optimized routes based on a routing cost function which includes route length, fault status, and traffic congestion all at the same time. We present an efficient implementation of cost based deflection routing and investigate its communication performance.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Coppola M, Grammatikakis MD, Locatelli R, Maruccia G, Pieralisi L (2008) Design of cost-efficient interconnect processing units—Spidergon STNoC. CRC Press, Boca Raton

    Book  Google Scholar 

  2. Furber S (2006) Living with failure: lessons from nature. In: Proceedings of the European test symposium (ETS), pp 1–4

    Google Scholar 

  3. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the design automation conference (DAC), pp 684–689

    Google Scholar 

  4. Penolazzi S, Jantsch A (2006) A high level power model for the Nostrum NoC. In: Proceedings of the Euromicro conference on digital system design (DSD), pp 673–676

    Google Scholar 

  5. Lu Z, Zhong M, Jantsch A (2006) Evaluation of on-chip networks using deflection routing. In: Proceedings of the great lakes symposium on VLSI (GLSVLSI), pp 296–301

    Google Scholar 

  6. Raik J, Ubar R, Govind V (2007) Test configurations for diagnosing faulty links in NoC switches. In: Proceedings of the European test symposium (ETS), pp 29–34

    Google Scholar 

  7. Grecu C, Ivanov A, Saleh R, Sogomonyan ES, Pande PP (2006) On-line fault detection and location for NoC interconnects. In: Proceedings of the international on-line testing symposium (IOLTS), pp 145–150

    Google Scholar 

  8. Alaghi A, Karimi N, Sedghi M, Navabi Z (2007) Online NoC switch fault detection and diagnosis using a high level fault model. In: Proceedings of the international symposium on defect and fault-tolerance in VLSI systems (DFT), pp 21–29

    Google Scholar 

  9. Kohler A, Radetzki M (2009) Fault-tolerant architecture and deflection routing for degradable NoC switches. In: Proceedings of the 3rd ACM/IEEE international symposium on networks-on-chip (NOCS), pp 22–31

    Google Scholar 

  10. Bogdan P, Dumitras T, Marculescu R (2007) Stochastic communication: a new paradigm for fault-tolerant networks-on-chip. Hindawi VLSI design, pp 17

    Google Scholar 

  11. Mediratta SD, Draper J (2007) Performance evaluation of probe-send fault-tolerant network-on-chip router. In: Proceedings of the conference on application-specific systems, architectures and processors (ASAP), pp 69–75

    Google Scholar 

  12. Wu J, Wang D (2002) Fault-tolerant and deadlock-free routing in 2-d meshes using rectilinear-monotone polygonal fault blocks. In: Proceedings of the international conference on parallel processing, pp 247–254

    Google Scholar 

  13. Hu J, Marculescu R (2004) Dyad—smart routing for networks-on-chip. In: Proceedings of the design automation conference (DAC), pp 260–263

    Google Scholar 

  14. Zhang Z, Greiner A, Taktak S (2008) A reconfigurable routing algorithm for a fault-tolerant 2d-mesh network-on-chip. In: Proceedings of the design automation conference (DAC), pp 441–446

    Google Scholar 

  15. Li M, Zeng Q-A, Jone W-B (2006) DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of the design automation conference (DAC), pp 849–852

    Google Scholar 

  16. Nilsson E, Millberg M, Öberg J, Jantsch A (2003) Load distribution with the proximity congestion awareness in a network on chip. In: Proceedings of the design, automation and test in Europe (DATE), pp 1126–1127

    Google Scholar 

  17. Kuhn HW (1955) The Hungarian method for the assignment problem. Nav Res Logist Quart 2:83–97

    Article  Google Scholar 

  18. IEEE Standard 1666 (2005) SystemC 2.1 language reference manual. IEEE Standards Association, Piscataway

    Google Scholar 

  19. Open SystemC Initiative (2008) OSCI TLM-2.0 user manual. Software version TLM-2.0. Document version JA22, http://www.systemc.org

  20. Radetzki M (2006) SystemC TLM transaction modelling and dispatch for active objects. In: Proceedings of the forum on design languages (FDL), pp 203–209

    Google Scholar 

  21. Radetzki M, Salimi Khaligh R (2008) Accuracy-adaptive simulation of transaction level models. In: Proceedings of the design automation and test in Europe (DATE), pp 788–791

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Martin Radetzki .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Radetzki, M., Kohler, A. (2011). Cost-Based Deflection Routing for Intelligent NoC Switches. In: Conti, M., Orcioni, S., Martínez Madrid, N., Seepold, R. (eds) Solutions on Embedded Systems. Lecture Notes in Electrical Engineering, vol 81. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0638-5_6

Download citation

  • DOI: https://doi.org/10.1007/978-94-007-0638-5_6

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-0637-8

  • Online ISBN: 978-94-007-0638-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics