Abstract
In this paper, we will give a short motivation for the use of symbolic methods for model order reduction and present some of these techniques. Furthermore, we will discuss the hierarchy usually at hand for circuit design and present a workflow for the exploitation of this hierarchy. By applying it to a simple circuit example, we will show how model order reduction (MOR) methods can be profitably employed.
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Notes
- 1.
In MNA contributions of components to the system typically are of the form \(A^T \cdot f(Bx),\) where A and B are incidence matrices describing the circuit topology and f is a function describing the behavior of the corresponding component. The same expression holds for submodels.
- 2.
x% error here means \({\frac{x}{100}}\) of the maximum magnitude of the reference solution, considered on the entire time interval: \({\frac{x}{100}}\cdot\sup_{t\in[t_0,t_1]}||v_F(t)||_{\infty}.\)
- 3.
The computations were executed on a Dual Quad Xeon E5420 with 2.5 MHz and 16 GB RAM.
- 4.
A ranking is a trade-off between accuracy and efficiency in computation time that estimates the influence of a term in the equation system on the system’s solution.
- 5.
One step provides sufficient accuracy here, since the sources are DC voltage sources.
- 6.
We performed some experiments with a higher number of iteration steps, but the gain of additional accuracy in comparison to the size of the larger system was rather marginal for a number of iteration steps bigger than five.
- 7.
As we are reducing only the single subsystem, this error bound is not limiting the error of the entire circuit’s output Vout to the given values (see Sect. 15.4 and Algorithm 1 for further details).
- 8.
We chose the more accurate model with 66 equations, see Fig. 15.10.
- 9.
A test bench is a simulation test environment. Here, one could take all the rest of the entire circuit as test bench.
- 10.
Of course, one could record the currents as well.
- 11.
By providing the voltages at all k ports, they work as the input to the subsystem. Then the currents flowing into the subsystem at the k ports are defined as the output and will be controlled by the specified error bound.
- 12.
The respective flows are directed towards the interior of each pipe.
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Acknowledgements
The work reported in this paper has been carried out within the project SyreNe (Systemreduktion für IC Design in der Nanoelektronik [19], Grant no. 03LAPAE6) which is supported by the German Federal Ministry of Education and Research (BMBF). The first named author wants to thank his thesis advisor G.-M. Greuel for additional support. Responsibility for the contents of this publication rests with the authors.
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Schmidt, O., Halfmann, T., Lang, P. (2011). Coupling of Numerical and Symbolic Techniques for Model Order Reduction in Circuit Design. In: Benner, P., Hinze, M., ter Maten, E. (eds) Model Reduction for Circuit Simulation. Lecture Notes in Electrical Engineering, vol 74. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0089-5_15
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