Advertisement

A High Level Synthesis Flow Using Model Driven Engineering

  • Sebastien Le Beux
  • Laurent Moss
  • Philippe Marquet
  • Jean-Luc Dekeyser
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 73)

Abstract

This chapter presents a High Level Synthesis (HLS) flow dedicated to intensive signal processing applications. Model Driven Engineering (MDE) is the skeleton of this flow. The benefits of extending this software technology to hardware design are used to solve major difficulties encountered by usual HLS flows. Both users and designers of the flow take advantage of the MDE methodology, leading to a concrete and effective advancement in the HLS research domain. The flow is automated from UML specifications to VHDL code generation. It has been successfully evaluated for the design of a hardware accelerator dedicated to signal processing.

Keywords

High Level Synthesis Hardware accelerators Model Driven Engineering Intensive signal processing 

References

  1. 1.
    Alanen M, Lilius J, Porres I, Truscan D, Oliver I, Sandstrom K (2006) Design method support for domain specific soc design. In: Proceedings of the fourth workshop on model-based development of computer-based systems and third international workshop on model-based methodologies for pervasive and embedded software (MBD-MOMPES ’06), pp 25–32 Google Scholar
  2. 2.
    Atitallah RB, Piel E, Niar S, Marquet P, Dekeyser J-L (2007) Multilevel MPSoC simulation using an MDE approach. In: IEEE international SoC conference (SoCC 2007), Hsinchu, Taiwan Google Scholar
  3. 3.
    Bastoul C (2004) Code generation in the polyhedral model is easier than you think. In: PACT’13 IEEE international conference on parallel architecture and compilation techniques, Juan-les-Pins, France, pp 7–16 Google Scholar
  4. 4.
    Björklund D, Lilius J (2002) From UML behavioral descriptions to efficient synthesizable VHDL. In: Proceedings of the 20th IEEE Norchip conference Google Scholar
  5. 5.
    Boulet P (2007) Array-OL revisited, multidimensional intensive signal processing specification. Research report, RR-6113, INRIA Google Scholar
  6. 6.
    Chen P-S (1976) The entity-relationship model – toward a unified view of data. ACM Trans Database Syst 1(1):9–36 CrossRefGoogle Scholar
  7. 7.
    Coussy P, Gajski DD, Meredith M, Takach A (2009) An introduction to high-level synthesis. IEEE Des Test Comput 26(4):8–17 CrossRefGoogle Scholar
  8. 8.
    Coussy P, Morawiec A (eds) (2008) High-level synthesis: from algorithm to digital circuit. Springer, New York Google Scholar
  9. 9.
    Coyle FP, Thornton MA (2005) From UML to HDL: a model driven architectural approach to hardware–software co-design. In: Information systems: new generations conference (ISNG), pp 88–93 Google Scholar
  10. 10.
    Czarnecki K, Helsen S (2003) Classification of model transformation approaches. In: Proceeding of OOPSLA workshop on generative techniques in the context of model driven architecture Google Scholar
  11. 11.
    Devos H, Beyls K, Christiaens M, Van Campenhout J, Stroobandt D (2006) From loop transformation to hardware generation. In: Proceedings of the 17th ProRISC workshop, Veldhoven, pp 249–255 Google Scholar
  12. 12.
    Frigo J, Gokhale M, Lavenier D (2001) Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. In: Proceedings of the 2001 ACM/SIGDA ninth international symposium on field programmable gate arrays (FPGA), pp 134–140 Google Scholar
  13. 13.
    Glitia C, Boulet P (2008) High level loop transformations for multidimensional signal processing embedded applications. In: International symposium on systems, architectures, modeling, and simulation (SAMOS VIII), Samos, Greece Google Scholar
  14. 14.
    Guillou A-C, Quinton P, Risset T (2003) Hardware synthesis for multi-dimensional time. In: IEEE 14th international conference on application-specific systems, architectures and processors (ASAP ’03), The Hague, The Netherlands, pp 40–51 Google Scholar
  15. 15.
    Guo Z, Buyukkurt B, Najjar W, Vissers K (2005) Optimized generation of data-path from C codes for FPGAs. In: DATE ’05: proceedings of the conference on design, automation and test in Europe. IEEE Comput Soc, Washington, pp 112–117 Google Scholar
  16. 16.
    Gupta S, Dutt N, Gupta R, Nicolau A (2003) SPARK: a high-level synthesis framework for applying parallelizing compiler transformations. In: Intl conf on VLSI design, pp 461–466 Google Scholar
  17. 17.
    Kangas T, Kukkala P, Orsila H, Salminen E, Hännikäinen M, Hämäläinen TD, Riihimäki J, Kuusilinna K (2006) UML-based multiprocessor SoC design framework. ACM Trans Embed Comput Syst 5(2):281–320 CrossRefGoogle Scholar
  18. 18.
    Lanusse P, Gérard S, Terrier F (1998) Real-time modeling with UML: the ACCORD approach. In: UML 98: beyond the notation, Mulhouse, France Google Scholar
  19. 19.
    Lo J, Eggers S, Levy H, Tullsen D (1996) Compilation issues for a simultaneous multithreading processor. In: Proceedings of the first SUIF compiler workshop, pp 146–147 Google Scholar
  20. 20.
    Martin G, Lavagno L, Louis-Guerin J (2001) Embedded UML: a merger of real-time UML and co-design. In: Proceedings of the 9th international symposium on hardware/software codesign (CODES), pp 23–28 Google Scholar
  21. 21.
    Milder P, Franchetti F, Hoe JC, Puschel M (2008) Formal datapath representation and manipulation for implementing DSP transforms. In: 2008 45th ACM/IEEE design automation conference, Piscataway, NJ, USA, pp 385–90 Google Scholar
  22. 22.
    Nguyen KD, Sun Z, Thiagarajan PS, Wong W-F (2004) Model-driven SoC design via executable UML to SystemC. In: RTSS ’04: proceedings of the 25th IEEE international real-time systems symposium (RTSS ’04). IEEE Comput Soc, Washington, pp 459–468 CrossRefGoogle Scholar
  23. 23.
    Object Management Group (2007) A UML profile for MARTE. http://www.omgmarte.org
  24. 24.
    Object Management Group, Inc. (ed) (2005) (UML) profile for schedulability, performance, and time, version 1.1. http://www.omg.org/technology/documents/formal/schedulability.htm
  25. 25.
    Object Management Group, Inc. (ed) (2006) Final adopted OMG SysML specification. http://www.omg.org/cgi-bin/doc?ptc/06-0504
  26. 26.
    Püschel M, Moura JMF, Johnson J, Padua D, Veloso M, Singer B, Xiong J, Franchetti F, Gacic A, Voronenko Y, Chen K, Johnson RW, Rizzolo N (2005) SPIRAL: code generation for DSP transforms. Proc IEEE 93(2):232–275 CrossRefGoogle Scholar
  27. 27.
    Quadri IR, Meftali S, Dekeyser J-L (2009) From MARTE to dynamically reconfigurable FPGAs: introduction of a control extension in a model based design flow. Technical report, DART – INRIA Lille – Nord Europe – INRIA – CNRS: UMR8022 – Université des Sciences et Technologies de Lille - Lille I. http://hal.archives-ouvertes.fr/inria-00365061/PDF/RR-6862.pdf
  28. 28.
    Riccobene E, Scandurra P, Rosti A, Bocchio S (2006) A model-driven design environment for embedded systems. In: DAC ’06: proceedings of the 43rd annual conference on design automation. ACM, New York, pp 915–918 CrossRefGoogle Scholar
  29. 29.
    Rieder M, Steiner R, Berthouzoz C, Corthay F, Sterren T (2007) Synthesized UML, a practical approach to map UML to VHDL. Rapid integration of software engineering techniques. Springer, Berlin Google Scholar
  30. 30.
    Rinker R, Carter M, Patel A, Chawathe M, Ross C, Hammes J, Najjar WA, Böhm W (2001) An automated process for compiling dataflow graphs into reconfigurable hardware. IEEE Trans Very Large Scale Integr Syst 9(1):130–139 CrossRefGoogle Scholar
  31. 31.
    Schmidt DC (2006) Model-driven engineering. IEEE Comput 39(2):41–47 CrossRefGoogle Scholar
  32. 32.
    Seidewitz E (2003) What models mean. IEEE Softw 20(5):26–32 CrossRefGoogle Scholar
  33. 33.
    Selic B (1998) Using UML for modeling complex real-time systems. In: LCTES ’98: proceedings of the ACM SIGPLAN workshop on languages, compilers, and tools for embedded systems. Springer, London, pp 250–260 CrossRefGoogle Scholar
  34. 34.
    Thomas DE, Moorby PR (1998) The Verilog hardware description language, 4th edn. Kluwer Academic, Norwell MATHCrossRefGoogle Scholar
  35. 35.
    Vidal J, de Lamotte F, Gogniat G, Soulard P, Diguet J-P (2009) A co-design approach for embedded system modeling and code generation with UML and MARTE. In: design, automation and test in Europe conference and exhibition (DATE) Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Sebastien Le Beux
    • 1
  • Laurent Moss
    • 2
  • Philippe Marquet
    • 3
  • Jean-Luc Dekeyser
    • 3
  1. 1.Institut des Nanotechnologies de LyonEcole Centrale de LyonEcully CedexFrance
  2. 2.Ecole Polytechnique de MontréalMontréalCanada
  3. 3.LIFL and INRIA Lille Nord-EuropeVilleneuve d’AscqFrance

Personalised recommendations