Hybrid Heuristics for Optimizing Energy Consumption in Embedded Systems

  • Maha Idrissi Aouad
  • René Schott
  • Olivier Zendra
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 62)


In this paper, we propose new hybrid heuristics for memory management which outperform the best known existing heuristic (BEH). In fact, nearly from 76% up to 98% less energy consumption is recorded. Contrary to BEH, our hybrid heuristics do not require list sorting.


Tabu Search Tabu List Memory Management Memory Architecture Standard Benchmark 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    H. Ben Fradj, A. El Ouardighi, C. Belleudy, and M. Auguin. Energy aware memory architecture configuration. ACM SIGARCH Computer Architecture News, 2005.Google Scholar
  2. 2.
    H. Cassfie and C. Rochange. OTAWA, Open Tool for Adaptative WCET Analysis. In DATE, Nice, April 2007. Poster session.Google Scholar
  3. 3.
    M. Gendreau. An introduction to tabu search, volume 57. Kluwer Academic Publishers, Boston, MA, 2003.Google Scholar
  4. 4.
    M. Idrissi Aouad, R. Schott, and O. Zendra. A Tabu Search Heuristic for Scratch-Pad Memory Management. In Proc. of WASET, volume 64, April 2010.Google Scholar
  5. 5.
    M. Idrissi Aouad, R. Schott, and O. Zendra. Genetic Heuristics for Reducing Memory Energy Consumption in Embedded Systems. In Proc. of ICSOFT, July 2010. To appear.Google Scholar
  6. 6.
    M. Idrissi Aouad and O. Zendra. A Survey of Scratch-Pad Memory Management Techniques for low-power and -energy. In Proc. of ICOOOLPS, July 2007.Google Scholar
  7. 7.
    S. N. Sivanandam and S. N. Deepa. Introduction to Genetic Algorithms. Springer Publishing Company, Incorporated, 2007.Google Scholar
  8. 8.
    A. Tanenbaum. Architecture de l’ordinateur 5e fiedition. November 2005.Google Scholar
  9. 9.
    S.J.E. Wilton and N.P. Jouppi. Cacti: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 1996.Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Maha Idrissi Aouad
    • 1
  • René Schott
    • 2
  • Olivier Zendra
    • 1
  1. 1.INRIA Nancy - Grand Est / LORIAVillers-Lès-NancyFrance
  2. 2.IECN - LORIA, Nancy-Université, Université Henri PoincaréVandoeuvre-Lès-NancyFrance

Personalised recommendations