Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort

  • Sezer Gören
  • H. Fatih Ugurdag
  • Okan Palaz
Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 62)


High defect densities in self-assembled nanotechnology require defect tolerant design strategies. This article presents a heuristic that addresses the problem of mapping logic functions onto defective nanocrossbar structures. The heuristic is defect-aware, thus uses a defect map during the logic mapping process. The proposed algorithm involves a two-dimensional sort (2D-Sort) and is significantly faster than the previous works with defect-aware design flow approaches. This is mostly due to the fact that the search space in our case becomes smaller when a 2D-Sort is applied on both the logic function and crossbar tables.


Logic Function Product Term Defect Rate Logic Minimization High Defect Density 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    ACM/SIGDA benchmarks: 1993 LGSynth Benchmarks,
  2. 2.
    NAEIMI, H. 2005. A Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design. M.S. Thesis, Calif. Inst. Of Technology.Google Scholar
  3. 3.
    RAO, W., ORAILOGLU, A. AND KARRI, R. 2009. Logic Mapping in Crossbar-Based Nanoarchitectures. IEEE Design & Test of Computers, 26, 68–76.CrossRefGoogle Scholar
  4. 4.
    RATNER, M.A.AND RATNER, D. 2002. Nanotechnology: A Gentle Introduction to the Next Big Idea. Prentice Hall PTR.Google Scholar
  5. 5.
    SHUKLA, S. K. AND BAHAR, R. I. 2004. Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, Kluwer Academic Publishers, Boston, MA.Google Scholar
  6. 6.
    TAHOORI, M.B. 2005. A mapping algorithm for defect-tolerance of reconfigurable nanoarchitectures. In Proceedings of Int’l Conf. on Computer-Aided Design. 667–671.Google Scholar
  7. 7.
    ZHENG, Y. AND HUANG, C. 2009. Defect-aware Logic Mapping for Nanowire-based Programmable Logic Arrays via Satisfiability. In Proceedings of Conf. Design Automation and Test in Europe.Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Department of Computer EngineeringBahçesehir UniversityIstanbulTurkey

Personalised recommendations