Defect-Tolerant Logic Mapping for Nanocrossbars Based on Two-Dimensional Sort

Conference paper
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 62)

Abstract

High defect densities in self-assembled nanotechnology require defect tolerant design strategies. This article presents a heuristic that addresses the problem of mapping logic functions onto defective nanocrossbar structures. The heuristic is defect-aware, thus uses a defect map during the logic mapping process. The proposed algorithm involves a two-dimensional sort (2D-Sort) and is significantly faster than the previous works with defect-aware design flow approaches. This is mostly due to the fact that the search space in our case becomes smaller when a 2D-Sort is applied on both the logic function and crossbar tables.

Keywords

Logic Function Product Term Defect Rate Logic Minimization High Defect Density 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Department of Computer EngineeringBahçesehir UniversityIstanbulTurkey

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