Multi-Step Analog to Digital Converter Testing

  • Amir Zjajo
  • José Pineda de Gyvez
Part of the Analog Circuits and Signal Processing book series (ACSP)


Complex System-on-Chip (SoC) products include analog and mixed-signal IPs which needs to be testable. Since these IPs are embedded in the SoC, it is difficult to access all of their ports and as such existing test practices are not always applicable, or need to be revised. This implies also that test times need to be reduced to acceptable limits within the digital-testing time domain; it also implies the incorporation of Design-for-Testability (DfT), Built-in-Self-Test (BIST) and silicon debug techniques. For these SoCs, many of the tests exercised at final test are being migrated to wafer test, partly because of the need to deliver known good dies before packaging, and partly because of the need to lower analog test costs.

A typical test flow allocates test times to wafer test and final test. More traditionally, a wafer test consists primarily of dc tests with current/voltage checks per pin under most operating conditions and with the test limits properly adjusted and in some cases some low-frequency tests to ensure functionality. A wafer test is geared to check open/short circuits, dc biases, charge-pump currents, and logic leakage among other parameters. A final test consists of checking device functionality by exercising tests to cover important circuit parameters. However, with the advent of new packaging techniques and pressure on test costs, tra0ditional functional tests at package level are being pushed backwards to wafer level. Under this new scenario, wafer testing is performed to determine the true performance of the die independent of the packaging.


Test Stimulus Parasitic Capacitance Fault Coverage Automatic Test Equipment Gain Stage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 125.
    D.G. Haigh, B. Singh, A switching scheme for switched capacitor filters which reduces the effect of parasitic capacitances associated with switch control terminals. Proc IEEE Int Symp Circuits Syst 2(7), 586–589 (1983)Google Scholar
  2. 140.
    K. Bult, G. Geelen, A fast-settling CMOS Op Amp for SC circuits with 90-dB DC gain. IEEE J. Solid-State Circuits 25(6), 1379–1384 (1990)CrossRefGoogle Scholar
  3. 154.
    R. Hogervorst, J.H. Huijsing, Design of Low-Voltage Low-Power Operational Amplifier Cells (Kluwer, Dordrecht, 1999)Google Scholar
  4. 162.
    D.A. Johns, K. Martin, Analog Integrated Circuit Design (Wiley, New York, 1997)Google Scholar
  5. 218.
    T. M. Sounder, G.N. Stenbakken, A comprehensive approach for modeling and testing analog and mixed-signal devices. Proceedings of IEEE International Test Conference, pp. 169–176, 1990Google Scholar
  6. 219.
    N. Nagi, A. Chatterjee, A Balivada, J.A. Abraham, Fault-based automatic test generator for linear analog circuits. Proceedings of IEEE International Conference on Computer Aided Design, pp. 88–91, 1993Google Scholar
  7. 220.
    T. Koskinen, P.Y.K. Cheung, Hierarchical tolerance analysis using statistical behavioral models. IEEE Trans. Comput. Aided Design 15(5), 506–516 (1996)CrossRefGoogle Scholar
  8. 221.
    S.J. Spinks, C.D. Chalk, I.M. Bell, M. Zwolinski, Generation and verification of tests for analog circuits subject to process parameter deviations. J. Electron. Test.: Theor Appl. 20, 11–23 (2004)CrossRefGoogle Scholar
  9. 222.
    A. Zjajo, J. Pineda de Gyvez, Evaluation of signature-based testing of RF/analog circuits. Proceedings of IEEE European Test Symposium, pp. 62–67, 2005Google Scholar
  10. 223.
    R. Voorakaranam, S.S. Akbay, S. Bhattacharya, S. Cherubal, A. Chatterjee, Signature testing of analog and RF circuits: algorithms and methodology. IEEE Trans. Circuits Syst.-I: Fund. Theor. Appl. 54, 1018–1031 (2007)CrossRefGoogle Scholar
  11. 224.
    A. McKeon, A. Wakeling, Fault diagnosis in analog circuit using AI techniques. Proceedings of IEEE International Test Conference, pp. 118–123, 1989Google Scholar
  12. 225.
    L. Milor, V. Visvanathan, Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput.-Aided Design 8(2), 114–130 (1989)CrossRefGoogle Scholar
  13. 226.
    G. Devarayanadurg, M. Soma, Analytical fault modeling and static test generation for analog ICs. Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 44–47, 1994Google Scholar
  14. 227.
    Z. Wang, G. Gielen, W. Sansen, A novel method for the fault detection of analog integrated circuits. Proc. IEEE Int. Symp. Circuits Syst. 1, 347–350 (1994)Google Scholar
  15. 228.
    K. Saab, N. Ben-Hamida, B. Kaminska, Parametric fault simulation and test vector generation. Proceedings of IEEE Design, Automation and Test in Europe Conference, pp. 650–656, 2000Google Scholar
  16. 229.
    F. Liu, P.K. Nikolov, S. Ozev, Parametric fault diagnosis for analog circuits using a Bayesian framework. Proceedings of IEEE VLSI Test Symposium, pp. 272–277, 2006Google Scholar
  17. 230.
    J. Neyman, E. Pearson, On the problem of the most efficient tests of statistical hypotheses. Philos. Trans. R. Soc. Lond. A 231, 289–337 (1933)Google Scholar
  18. 231.
    A. Zjajo, J. Pineda de Gyvez, Analog automatic test pattern generation for quasi-static structural test. IEEE Transaction on Very Large Scale Integration (VLSI) Systems, accepted for publicationGoogle Scholar
  19. 232.
    E. Silva, J. Pineda de Gyvez, G. Gronthoud, Functional vs. multi-VDD testing of RF circuits.Proceedings of IEEE International Test Conference, 2005Google Scholar
  20. 233.
    M. Loève, Probability Theory (D. Van Nostrand, Princeton, NJ, 1960)zbMATHGoogle Scholar
  21. 234.
    J. Vlach, K. Singhal, Computer Methods for Circuit Analysis and Design (Van Nostrand Reinhold, New York, 1983)Google Scholar
  22. 235.
    K.E. Brenan, S.L. Campbell, L.R. Petzold, The Numerical Solution of Initial Value Problems in Ordinary Differential-Algebraic Equations (North Holland, New York, 1989)Google Scholar
  23. 236.
    J. Butcher, P. Chartier, Parallel general linear methods for stiff ordinary differential and differential algebraic equations. Appl. Numer. Math. 17, 213–222 (1995)zbMATHCrossRefMathSciNetGoogle Scholar
  24. 237.
    P.J. Rrabier, W.C. Rheinboldt, Techniques of scientific computing (part 4), in Handbook of Numerical Analysis, ed. by P.G. Ciarlet, vol. 8 (North Holland/Elsevier, Amsterdam, 2002), pp. 183–540Google Scholar
  25. 238.
    M. Gunther, U. Feldmann, CAD based electric modeling in Industry. Math. Comput. Simul 39, 573–582 (1995)CrossRefMathSciNetGoogle Scholar
  26. 239.
    M. Gunther, U. Feldmann, CAD based electric modeling in industry, Part I: mathematical structure and index of network equations. Surv. Math. Indus. 8, 97–129 (1999)MathSciNetGoogle Scholar
  27. 240.
    C. Tischendorf, Topological index calculation of DAEs in circuit simulation. Surv. Math. Indus. 8, 187–199 (1999)zbMATHMathSciNetGoogle Scholar
  28. 241.
    G. Ali, A. Bartel, M. Günther, Parabolic differential-algebraic models in electrical network design. Soc. Indus. Appl. Math. – J. Multiscale Model. Simul. 4, 813–838 (2005)zbMATHCrossRefGoogle Scholar
  29. 242.
    H.P. Tuinhout, S. Swaving, J. Joosten, A fully analytical MOSFET model parameter extraction approach. IEEE Proc. Microelectron. Test Struct. 1(1), 79–84 (1988)CrossRefGoogle Scholar
  30. 243.
    T.L. Chen, G. Gildenblat, Symmetric bulk charge linearization in the charge-sheet model. IEEE Electron. Lett. 37, 791–793 (2001)CrossRefGoogle Scholar
  31. 244.
    R. van Langevelde, A.J. Scholten, D.B.M. Klassen, MOS Model 11: Level 1102. Philips Research Technical Report 2004/85Google Scholar
  32. 245.
    M. Grigoriu, On the spectral representation method in simulation. Probab. Eng. Mech. 8, 75–90 (1993)CrossRefGoogle Scholar
  33. 246.
    H. Stark, W.J. Woods, Probability, Random Process and Estimation Theory for Engineers (Prentice-Hall, Englewood Cliffs, NJ, 1994)Google Scholar
  34. 247.
    R. Ghanem, P.D. Spanos, Stochastic Finite Element: A Spectral Approach (Springer, New York, 1991)zbMATHGoogle Scholar
  35. 248.
    P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, C. Spanos, Modeling within-die spatial correlation effects for process-design co-optimization. Proceedings of IEEE International Symposium on Quality of Electronic Design, pp. 516–521, 2005Google Scholar
  36. 249.
    J. Xiong, V. Zolotov, L. He, Robust extraction of spatial correlation. Proceedings of IEEE International Symposium on Physical Design, pp. 2–9, 2006Google Scholar
  37. 250.
    B.E. Stine, D.S. Boning, J.E. Chung, Analysis and decomposition of spatial variation in integrated circuit process and devices. IEEE Transaction on Semiconductor Manufacturing, pp. 24–41, 1997Google Scholar
  38. 251.
    A. Zjajo, J. Pineda de Gyvez, G. Gronthoud, Structural fault modeling and fault detection through Neyman-Pearson decision criteria for analog integrated circuits. J. Electron. Test.: Theor. Appl. 22, 399–409 (2006)CrossRefGoogle Scholar
  39. 252.
    S.D. Huss, R.S. Gyurcsik, Optimal ordering of analog integrated circuit tests to minimize test time. Proceedings of Design Automation Conference, pp. 494–499, 1991Google Scholar
  40. 253.
    IEEE Std. 1149.4-1999, Test Technology Technical Committee of the IEEE Computer Society, IEEE Standard for a Mixed-Signal Test Bus. Institute of Electrical and Electronic Engineers Inc.Google Scholar
  41. 254.
    G. Schafer, H. Sapotta, W. Dennerm, Block-oriented test strategy for analog circuits. Proceedings of IEEE European Solid-State Circuit Conference, pp. 217–220, 1991Google Scholar
  42. 255.
    M. Soma, A design for test methodology for active analog filters. Proceedings of IEEE International Test Conference, pp. 183–192, 1990Google Scholar
  43. 256.
    A.H. Bratt, R.J. Harvey, A.P. Dorey, A.M.D. Richardson, Design for test structure to facilitate test vector application with low performance loss in non-test mode. Electron. Lett 4(4), 299–313 (1993)Google Scholar
  44. 257.
    D. Vazquez, J.L. Huertas, A. Rueda, A new strategy for testing analog filters. Proceedings of IEEE VLSI Test Symposium, pp. 36–41, 1994Google Scholar
  45. 258.
    D. Vazquez, J.L. Huertas, A. Rueda, Reducing the impact of DfT on the performance of analog integrated circuits: improved SW-OPAMP design. Proceedings of IEEE VLSI Test Symposium, pp. 42–48, 1996Google Scholar
  46. 259.
    B. Vinnakota, R. Harjani, DFT for digital detection of analog parametric faults in SC filters. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 19(7), 789–798 (2000)CrossRefGoogle Scholar
  47. 260.
    E. Peralias, A. Rueda, J.L. Huertas, A DFT technique for analog-to-digital converters with digital correction. Proceedings of IEEE VLSI Test Symposium, pp. 302–307, 1997Google Scholar
  48. 261.
    J. Pineda de Gyvez, G. Gronthoud, R. Amine, VDD Ramp Testing for RF Circuits. Proceedings of IEEE International Test Conference, pp. 651–658, 2003Google Scholar
  49. 262.
    A. Zjajo, J. Pineda de Gyvez, G. Gronthoud, A DC approach for detection and simulation of parametric faults in analog and mixed-signal circuits. Proceedings of IEEE International Mixed-Signal Testing Workshop, pp. 155–164, 2005Google Scholar
  50. 263.
    A. Zjajo, H.J. Bergveld, R. Schuttert, J. Pineda de Gyvez, Power-scan chain: design for analog testability. Proceedings of International Test Conference, 2005Google Scholar
  51. 264.
    S. Somayayula, E. Sanchez-Sinencio, J. Pineda de Gyvez, Analog fault diagnosis based on ramping power supply current signature. IEEE Trans. Circuits Syst.-II 43(10), 703–712 (1996)CrossRefGoogle Scholar
  52. 265.
    S. Tabatabaei, A. Ivanov, A built-in current monitor for testing analog circuit blocks. Proc. IEEE Int. Symp. Circuits Syst. 2, 109–114 (1999)Google Scholar
  53. 266.
    J.R. Vazquez, J. Pineda de Gyvez, Built-in current sensor for ΔIDDQ testing. IEEE J. Solid-State Circuits 39(3), 511–518 (2004)CrossRefGoogle Scholar
  54. 267.
    IEEE Std. 1149.1-2001, Test Technology Technical Committee of the IEEE Computer Society, IEEE Standard Test Access Port and Boundary-Scan Architecture. Institute of Electrical and Electronic Engineers Inc.Google Scholar
  55. 268.
    J. Galan, R.G. Carvajal, A. Torralba, F. Munoz, J. Ramirez-Angulo, A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range. IEEE Trans. Circuits Syst. 52(2), 283–291 (2005)CrossRefGoogle Scholar
  56. 269.
    G. Chang, A. Rofougaran, K. Mong-Kai, A.A. Abidi, H. Samueli, A low-power cmos digitally-synthesized 0–13 MHZ sinewave generator. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 32–33, 1994Google Scholar
  57. 270.
    B. Dufort, G.W. Roberts, On-chip analog signal generation for mixed-signal built-in-self-test. IEEE J. Solid-State Circuits 33(3), 318–330 (1999)CrossRefGoogle Scholar
  58. 271.
    J. Huang, K. Cheng, A sigma-delta modulation based BIST scheme for mixed-signal circuits. Proceedings of IEEE Design Automation Conference, pp. 605–610, 2000Google Scholar
  59. 272.
    A.K. Lu, G.W. Roberts, D. Johns, A high quality analog oscillator using oversampling D/A conversion techniques. IEEE Trans. Circuits Syst. II 41(7), 437–444 (1994)zbMATHCrossRefGoogle Scholar
  60. 273.
    M.J. Barragan, D. Vazquez, A. Rueda, J.L. Huertas, On-chip analog sinewave generator with reduced circuitry resources. Proceedings of IEEE Midwest Symposium on Circuits and Systems, pp. 638–642, 2006Google Scholar
  61. 274.
    Y.P. Tsividis, Integrated continuous-time filter design-an overview. IEEE J. Solid-State Circuits 29(3), 166–176 (1994)CrossRefGoogle Scholar
  62. 275.
    A.M. Durham, J.B. Hughes, W. Redman-White, Circuit architectures for high linearity monolithic continuous-time filtering. IEEE Trans. Circuits Syst.−II 39(9), 651–657 (1992)zbMATHCrossRefGoogle Scholar
  63. 276.
    R. Gharpurey, N. Yanduru, F. Dantoni, P. Litmanen, G. Sirna, T. Mayhugh, C. Lin, I. Deng, P. Fontaine, F. Lin, A direct conversion receiver for the 3G WCDMA standard. Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 239–242, 2002Google Scholar
  64. 277.
    S. Lindfors, J. Jussila, K. Halonen, L. Siren, A 3-V continuous-time filter with on-chip tuning for IS-95. IEEE J. Solid-State Circuits 34(8), 1150–1154 (1999)CrossRefGoogle Scholar
  65. 278.
    J.K. Pyykönen, A low distortion wideband active-RC filter for a multicarrier base station transmitter. Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 244–247, 2001Google Scholar
  66. 279.
    H. Khorramabadi, M.J. Tarsia, N.S. Woo, Baseband filters for IS-95 CDMA receiver applications featuring digital automatic frequency tuning. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 172–173, 1996Google Scholar
  67. 280.
    T. Salo, S. Lindfors, T. Hollman, K. Halonen, Programmable direct digital tuning circuit for a continuous-time filter. Proceedings of the European Solid-State Circuits Conference, pp. 168–171, 2000Google Scholar
  68. 281.
    S. Lindfors, T. Hollman, T. Salo, K. Halonen, A 2.7V CMOS GSM/WCDMA continuous-time filter with automatic tuning. Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 9–12, 2001Google Scholar
  69. 282.
    Y. Tsividis, Continuous-time filters in telecommunications chips. IEEE Communications Magazine, pp. 132–137, 2001Google Scholar
  70. 283.
    Z. Czarnul, Modification of Banu-Tsividis continuous-time integrator structure. IEEE Trans. Circuits Syst. 33(7), 714–716 (1986)CrossRefGoogle Scholar
  71. 284.
    U.-K. Moon, B.-S. Song, Design of a low-distortion 22-kHz fifth-order Bessel filter. IEEE J. Solid-State Circuits 28(12), 1254–1264 (1993)CrossRefGoogle Scholar
  72. 285.
    A. Yoshizawa, Y.P. Tsividis, Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers. IEEE J. Solid-State Circuits 37(3), 357–364 (2002)CrossRefGoogle Scholar
  73. 286.
    A. Yoshizawa, Design considerations for large dynamic range MOSFET-C filters for direct conversion receivers. Proceedings of the European Solid-State Circuits Conference, pp. 655–658, 2002Google Scholar
  74. 287.
    B. Nauta, A CMOS transconductance-C filter technique for very high frequencies. IEEE J. Solid-State Circuits 27(2), 142–153 (1992)CrossRefGoogle Scholar
  75. 288.
    S. Lindfors, K. Halonen, M. Ismail, A 2.7-V elliptical MOSFET-Only gmC-OTA filter. IEEE Trans. Circuits Syst.−II 47(2), 89–95 (2000)CrossRefGoogle Scholar
  76. 290.
    T. Itakura, T. Ueno, H. Tanimoto, A. Yasuda, R. Fujimoto, T. Arai, H. Kokatsu, A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced Gm-C filter IC. IEEE J. Solid-State Circuits 34(8), 1155–1159 (1999)CrossRefGoogle Scholar
  77. 291.
    T.C. Kuo, B.B. Lusignan, A very low power channel select filter for IS-95 CDMA receiver with on-chip tuning. IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 244–247, 2000Google Scholar
  78. 292.
    K. Halonen, S. Lindfors, J. Jussila, L. Siren, A 3V GmC-filter filter with on-chip tuning for CDMA. Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 83–86, 1997Google Scholar
  79. 293.
    C.A. Laber, P.R. Gray, A 20-MHz sixth-order BiCMOS Parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels. IEEE J. Solid-State Circuits 27(4), 462–470 (1993)CrossRefGoogle Scholar
  80. 294.
    B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, New York, 2001)Google Scholar
  81. 297.
    G.M. Jacobs, D.J. Allstot, R.W. Brodersen, P.R. Gray, Design techniques for MOS switched-capacitor ladder filters. IEEE Trans. Circuits Syst. 25(12), 1014–1021 (1978)CrossRefGoogle Scholar
  82. 298.
    A. Fettweis, D. Herbst, B. Hoefflinger, J. Pandel, R. Schweer, MOS switched capacitor filters using voltage inverter switches. IEEE Trans. Circuits Syst. 27(6), 527–538 (1980)CrossRefGoogle Scholar
  83. 299.
    F. Montecchi, On design of switched-capacitor filters with the voltage-inverter switch approach. Proc. IEEE Int. Symp. Circuits Syst. 2, 1479–1482 (1988)Google Scholar
  84. 300.
    R. Gregorian, G.C. Temes, Analog MOS Integrated Circuits for Signal Processing (Wiley, New York, 1986)Google Scholar
  85. 301.
    K. Martin, A.S. Sedra, Exact design of switched-capacitor bandpass filters using coupled-biquad structures. IEEE Trans Circuits Syst 27(6), 469–478 (1980)CrossRefGoogle Scholar
  86. 302.
    K. Martin, A.S. Sedra, Effects of the Op-Amp finite gain and bandwidth on the performance of switched-capacitor filters. IEEE Trans Circuits Syst 28(8), 822–829 (1981)CrossRefGoogle Scholar
  87. 303.
    A. Baschirotto, F. Severi, R. Castello, A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology. IEEE J. Solid-State Circuits 35(8), 1215–1219 (2000)CrossRefGoogle Scholar
  88. 304.
    A.D. Plaza, High-frequency switched-capacitor filter using unity-gain buffers. IEEE J. Solid-State Circuits 21(8), 470–477 (1986)CrossRefGoogle Scholar
  89. 305.
    C.Y. Wu, P.H. Lu, M.K. Tsai, Design techniques for high-frequency CMOS switched-capacitor filters using non-Op-Amp-based unity-gain amplifiers. IEEE J. Solid-State Circuits 26(4), 1460–1466 (1991)Google Scholar
  90. 306.
    B.K. Thandri, S.J. Silva-Martinez, F. Maloberti, A feedforward compensation scheme for high gain wideband amplifiers. Proceedings of IEEE International Conference on Electronics, Circuits and Systems, pp. 1115–1118, 2001Google Scholar
  91. 307.
    S. Pavan, Y. Tsividis, High Frequency Continuous Time Filters in Digital CMOS Processes (Kluwer, Boston, 2000)Google Scholar
  92. 308.
    Y. Tsividis, Y. Papananos, Continuous-time filters using buffer with gain lower than unity. IEEE Electron Lett 30(8), 629–630 (1994)CrossRefGoogle Scholar
  93. 309.
    J.S. Silva-Martinez, M. Steyaert, W. Sansen, High-Performance CMOS Continuous-Time Filters (Kluwer, Boston, 1993)Google Scholar
  94. 310.
    B. Nauta, Analog CMOS Filters for Very High Frequencies (Kluwer, Boston, 1993)Google Scholar
  95. 313.
    R. Schaumann, M.S. Ghausi, K.R. Laker, Design of Analog Filters (Prentice-Hall, Englewood Cliffs, NJ, 1990)Google Scholar
  96. 314.
    F. Maloberti, F. Montecchi, G. Torelli, E. Halasz, Bilinear design of fully differential switched-capacitor ladder filters. IEE Proc Electro Circuits Syst 132, 266–272 (1985)CrossRefGoogle Scholar
  97. 315.
    M. Maymandi-Nejad, M. Sachdev, Continuous-time common mode feedback technique for sub 1V analogue circuits. IEEE Electron Lett 38, 1408–1409 (2002)CrossRefGoogle Scholar
  98. 317.
    K.-H. Loh, D.L. Hiser, W.J. Adams, R.L. Geiger, A versatile digitally controlled continuous-time filter structure with wide-range and fine resolution capability. IEEE Trans Circuit Syst II 39(7), 265–276 (1992)CrossRefGoogle Scholar
  99. 327.
    F. Azais, S. Bernard, Y. Bertrand, M. Renovell, Towards an ADC BIST scheme using the histogram test technique. Proceedings of IEEE European Test Workshop, pp. 53–58, 2000Google Scholar
  100. 333.
    IEEE 1057 Standard for Digitizing Waveform Recorders, 1994Google Scholar
  101. 334.
    IEEE 1241 Standard for Analog-to-Digital Converters, 2000Google Scholar
  102. 335.
    M. Vanden Bossche, J. Schoukens, J. Eenneboog, Dynamic testing and diagnostics of A/D converters. IEEE Trans Circuits Syst 33(8), 775–785 (1986)CrossRefGoogle Scholar
  103. 336.
    J. Doernberg, H.-S. Lee, D.A. Hodges, Full-speed testing of A/D converters. IEEE J. Solid-State Circuits 19(6), 820–827 (1984)CrossRefGoogle Scholar
  104. 337.
    N. Giaquinto, A. Trotta, Fast and accurate ADC testing via an enhanced sine wave fitting algorithm. IEEE Trans. Instrum. Meas. 46(2), 1020–1024 (1997)CrossRefGoogle Scholar
  105. 338.
    F. Alegria, P. Arpaia, A.M. da Cruz Serra, P. Daponte, ADC histogram test by triangular small-waves. Proc IEEE Instrum Meas Technol Conf 3, 1690–1695 (2001)Google Scholar
  106. 339.
    L. Jin, K. Parthasarathy, T. Kuyel, D. Chen, R.L. Geiger, Linearity testing of precision analog-to-digital converters using stationary nonlinear inputs. Proceedings of IEEE International Test Conference, pp. 218–227, 2003Google Scholar
  107. 340.
    L. Jin, D. Chen, R. Geiger, SEIR linearity testing of precision A/D converters in nonstationary environments with center-symmetric interleaving. IEEE Trans. Instrum. Meas. 56(5), 1776–1785 (2007)CrossRefMathSciNetGoogle Scholar
  108. 341.
    E. Korhonen, J. Häkkinen, J. Kostamovaara, A robust algorithm to identify the test stimulus in histogram-based A/D converter testing. IEEE Trans. Instrum. Meas. 56(6), 2369–2374 (2007)CrossRefGoogle Scholar
  109. 344.
    X. Sheng, H. Kerkhoff, A. Zjajo, G. Gronthoud, Exploring dynamics of embedded ADC through adapted digital input stimuli. Proceedings of IEEE International Workshop on Mixed-Signals, Sensors, and Systems Test, pp. 1–7, 2008Google Scholar
  110. 345.
    X. Sheng, H. Kerkhoff, A. Zjajo, G. Gronthoud, Time-modulo reconstruction algorithms for cost-efficient A/D converter multi-site test. IEEE European Test Symposium, 2009, accepted for publicationGoogle Scholar
  111. 346.
    F.H. Irons, D.M. Hummels, The modulo time plot-a useful data acquisition diagnostic tool. IEEE Trans. Instrum. Meas. 45(3), 734–738 (1996)CrossRefGoogle Scholar
  112. 347.
    K. Bowman, J. Meindl, Impact of Within-die parameter fluctuations on the future maximum clock frequency distribution. Proceedings of IEEE Custom Integrated Circuits Conference, pp. 229–232, 2001Google Scholar
  113. 348.
    C. Michael, M. Ismail, Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits (Kluwer, Boston, 1993)Google Scholar
  114. 349.
    P.R. Gray, R.G. Meyer, Analysis and Design of Analog Integrated Circuits (Wiley, New York, 1984)Google Scholar
  115. 350.
    A. Demir, E. Liu, A. Sangiovanni-Vincentelli, Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations. Proceedings of IEEE/ACM Interanational Conference on Computer Aided Design, pp. 598–603, 1994Google Scholar
  116. 351.
    R. López-Ahumada, R. Rodríguez-Macías, FASTEST: a tool for a complete and efficient statistical evaluation of analog circuits. DC analysis. Analog Integr Circuits Signal Process, 29(3), 201–212 (2001)Google Scholar
  117. 353.
    J. Vlach, K. Singhal, Computer Methods for Circuit Analysis and Design (Van Nostrand Reinhold, New York, 1983)Google Scholar
  118. 354.
    L.O. Chua, C.A. Desoer, E.S. Kuh, Linear and Nonlinear Circuits (Mc Graw-Hill, New York, 1987)zbMATHGoogle Scholar
  119. 355.
    L. Arnold, Stochastic Differential Equations: Theory and Application (Wiley, New York, 1974)Google Scholar
  120. 356.
    A. Sangiovanni-Vincentelli, Circuit Simulation, in Computer Design Aids for VLSI Circuits (Sijthoff & Noordhoff, The Netherlands, 1980)Google Scholar
  121. 357.
    A.S. Hodel, S.T. Hung, Solution and applications of the lyapunov equation for control systems. IEEE Trans. Ind. Electron. 39(3), 194–202 (1992)CrossRefGoogle Scholar
  122. 358.
    R.H. Bartels, G.W. Stewart, Solution of the matrix equation AX+XB=C. Commun Assoc Comput Machin 15, 820–826 (1972)Google Scholar
  123. 359.
    N.J. Higham, Perturbation theory and backward error for AX−XB=C. BIT Numer Math 33, 124–136 (1993)zbMATHCrossRefMathSciNetGoogle Scholar
  124. 360.
    T. Penzl, Numerical solution of generalized Lyapunov equations. Adv. Comput. Math. 8, 33–48 (1998)zbMATHCrossRefMathSciNetGoogle Scholar
  125. 361.
    G.H. Golub, C.F. van Loan, Matrix Computations (Johns Hopkins University Press, Baltimore, 1996)zbMATHGoogle Scholar
  126. 362.
    V. Sima, Algorithms for Linear-Quadratic Optimization, Vol. 200, Pure and Applied Mathematics (Marcel Dekker, New York, 1996)Google Scholar
  127. 363.
    P. Benner, E. Quintana-Orti, Solving stable generalized lyapunov equations with the matrix sign function. Numer Algebra 20, 75–100 (1999)zbMATHCrossRefMathSciNetGoogle Scholar
  128. 364.
    I. Jaimoukha, E. Kasenally, Krylov subspace methods for solving large lyapunov equations. SIAM J. Numer. Anal. 31, 227–251 (1994)zbMATHCrossRefMathSciNetGoogle Scholar
  129. 365.
    E. Wachspress, Iterative solution of the lyapunov matrix equation. Appl. Math. Lett. 1, 87–90 (1998)CrossRefMathSciNetGoogle Scholar
  130. 366.
    J. Li, F. Wang, J. White, An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect. Proceedings of IEEE/ACM Design Automation Conference, pp. 1–6, 1999Google Scholar
  131. 367.
    The Numerics in Control Network, Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Delft University of TechnologyDelftThe Netherlands
  2. 2.Eindhoven University of Technology, and NXP SemiconductorsEindhovenThe Netherlands

Personalised recommendations