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Multi-Step Analog to Digital Converter Testing

  • Amir Zjajo
  • José Pineda de Gyvez
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

Complex System-on-Chip (SoC) products include analog and mixed-signal IPs which needs to be testable. Since these IPs are embedded in the SoC, it is difficult to access all of their ports and as such existing test practices are not always applicable, or need to be revised. This implies also that test times need to be reduced to acceptable limits within the digital-testing time domain; it also implies the incorporation of Design-for-Testability (DfT), Built-in-Self-Test (BIST) and silicon debug techniques. For these SoCs, many of the tests exercised at final test are being migrated to wafer test, partly because of the need to deliver known good dies before packaging, and partly because of the need to lower analog test costs.

A typical test flow allocates test times to wafer test and final test. More traditionally, a wafer test consists primarily of dc tests with current/voltage checks per pin under most operating conditions and with the test limits properly adjusted and in some cases some low-frequency tests to ensure functionality. A wafer test is geared to check open/short circuits, dc biases, charge-pump currents, and logic leakage among other parameters. A final test consists of checking device functionality by exercising tests to cover important circuit parameters. However, with the advent of new packaging techniques and pressure on test costs, tra0ditional functional tests at package level are being pushed backwards to wafer level. Under this new scenario, wafer testing is performed to determine the true performance of the die independent of the packaging.

Keywords

Test Stimulus Parasitic Capacitance Fault Coverage Automatic Test Equipment Gain Stage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Delft University of TechnologyDelftThe Netherlands
  2. 2.Eindhoven University of Technology, and NXP SemiconductorsEindhovenThe Netherlands

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