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Implementation of a High-speed Time-interleaved ADC

  • Simon Louwsma
  • Ed van Tuijl
  • Bram Nauta
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

Chapter 4 describes the actual implementation of a high-speed time-interleaved ADC based on the design choices described in this book. Since timing calibration is hard to implement, a switch-driver circuit with low skew is introduced, such that timing calibration is not needed.

The sub-ADCs consist of two 6 bits SA-ADCs, a DAC and an amplifier to achieve a good power efficiency, while increasing the maximum sample-rate over that of a single 10 bits SA-ADC.

Offset and gain calibrations are performed in the analog domain to avoid power-consuming digital operations and to keep the full input range available.

The chapter ends with a description of the measurement results: The ADC achieves a sample-rate of 1.8 GS/s with 7.9 ENOB and an ERBW of 1 GHz, while the power efficiency is 1 pJ/conversion-step. At an input frequency of 3.6 GHz, the SNDR is still 6.5 ENOB and total timing error including jitter is only 0.4 ps RMS. At a sample-rate of 1.35 GS/s, a FoM of 0.6 pJ/conversion step is achieved. This proves that the specifications stated in the beginning of this chapter are feasible.

Keywords

Parasitic Capacitance Clock Signal Residue Signal Comparator Decision CMOS Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Bibliography

  1. [1]
    A.M. Abo, Design for reliability of low-voltage, switched-capacity circuits. Ph.D. Thesis, University of California, Berkeley, 1999 Google Scholar
  2. [2]
    A.M. Abo, P.R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 34(5), 599–606 (1999) CrossRefGoogle Scholar
  3. [3]
    B.K. Ahuja, An improved frequency compensation technique for CMOS operational amplifiers. IEEE J. Solid-State Circuits 18(6), 629–633 (1983) MathSciNetCrossRefGoogle Scholar
  4. [10]
    T.B. Cho, P.R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J. Solid-State Circuits 30(3), 166–172 (1995) CrossRefGoogle Scholar
  5. [16]
    S.K. Gupta, M.A. Inerfield, J. Wang, A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-MAW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J. Solid-State Circuits 41(12), 2650–2657 (2006) CrossRefGoogle Scholar
  6. [18]
    C.-C. Hsu, F.-C. Huang, C.-Y. Shih, C.C. Huang, Y.-H. Lin, C.-C. Lee, B. Razavi, An 11 b 800 MS/s time-interleaved ADC with digital background calibration, in ISSCC Dig. Tech. Papers (2007), pp. 464–465 Google Scholar
  7. [22]
    F. Kuttner, A 1.2 V 10 b 20 MSample/s non-binary successive approximation ADC in 0.13 μm CMOS, in ISSCC Dig. Tech. Papers (2002), pp. 176–177 Google Scholar
  8. [24]
    S.M. Louwsma, E.J.M. van Tuijl, M. Vertregt, B. Nauta, A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS, in Proc. ESSCIRC (2004), pp. 343–346 Google Scholar
  9. [25]
    S.M. Louwsma, E.J.M. van Tuijl, M. Vertregt, B. Nauta, A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS, in Proceedings of the Symposium on Very Large Scale Integration (VLSI) Circuits (2007), pp. 62–63 Google Scholar
  10. [27]
    S.M. Louwsma, A.J.M. van Tuijl, M. Vertregt, B. Nauta, A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS. IEEE J. Solid-State Circuits 43(4), 778–786 (2008) CrossRefGoogle Scholar
  11. [33]
    K. Nagaraj, D.A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, T.R. Viswanathan, A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid-State Circuits 35(12), 1760–1768 (2000) CrossRefGoogle Scholar
  12. [34]
    Y. Nakagome, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, Y. Kawamoto, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda, K. Itoh, Experimental 1.5-V 64-Mb DRAM. IEEE J. Solid-State Circuits 26(4), 465–472 (1991) CrossRefGoogle Scholar
  13. [36]
    B. Nikolić, V.G. Oklobdžija, V. Stojanović, W. Jia, J.K.S. Chiu, M.M.T. Leung, Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Solid-State Circuits 35(6), 876–884 (2000) CrossRefGoogle Scholar
  14. [40]
    K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, A. Montijo, A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS, in ISSCC Dig. Tech. Papers (2003), pp. 318–496 Google Scholar
  15. [42]
    D. Schinkel, E. Mensink, E.A.M. Klumperink, A.J.M. van Tuijl, B. Nauta, A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time, in ISSCC Dig. Tech. Papers (2007), pp. 314–315 Google Scholar
  16. [47]
    R.C. Taft, P.A. Francese, M.R. Tursi, O. Hidri, A. MacKenzie, T. Hoehn, P. Schmitz, H. Werker, A. Glenny, A 1.8 V 1.0 GS/s 10 b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency, in ISSCC Dig. Tech. Papers (2009), pp. 78–79 Google Scholar
  17. [49]
    R.C.H. van de Beek, High-speed low-jitter frequency multiplication in CMOS. Ph.D. dissertation, University of Twente, 2004 Google Scholar
  18. [55]
    A.J.M. van Tuijl, personal communication Google Scholar
  19. [61]
    B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid-State Circuits 39(7), 1148–1158 (2004) CrossRefGoogle Scholar
  20. [63]
    K.L.J. Wong, C.K.K. Yang, Offset compensation in comparators with minimum input-referred supply noise. IEEE J. Solid-State Circuits 39(5), 837–840 (2004) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Axiom ICEnschedeNetherlands
  2. 2.Axiom IC/University of TwenteEnschedeNetherlands
  3. 3.MESA+ InstituteUniversity of TwenteEnschedeNetherlands

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