Implementation of a High-speed Time-interleaved ADC

  • Simon Louwsma
  • Ed van Tuijl
  • Bram Nauta
Part of the Analog Circuits and Signal Processing book series (ACSP)


Chapter 4 describes the actual implementation of a high-speed time-interleaved ADC based on the design choices described in this book. Since timing calibration is hard to implement, a switch-driver circuit with low skew is introduced, such that timing calibration is not needed.

The sub-ADCs consist of two 6 bits SA-ADCs, a DAC and an amplifier to achieve a good power efficiency, while increasing the maximum sample-rate over that of a single 10 bits SA-ADC.

Offset and gain calibrations are performed in the analog domain to avoid power-consuming digital operations and to keep the full input range available.

The chapter ends with a description of the measurement results: The ADC achieves a sample-rate of 1.8 GS/s with 7.9 ENOB and an ERBW of 1 GHz, while the power efficiency is 1 pJ/conversion-step. At an input frequency of 3.6 GHz, the SNDR is still 6.5 ENOB and total timing error including jitter is only 0.4 ps RMS. At a sample-rate of 1.35 GS/s, a FoM of 0.6 pJ/conversion step is achieved. This proves that the specifications stated in the beginning of this chapter are feasible.


Parasitic Capacitance Clock Signal Residue Signal Comparator Decision CMOS Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  1. 1.Axiom ICEnschedeNetherlands
  2. 2.Axiom IC/University of TwenteEnschedeNetherlands
  3. 3.MESA+ InstituteUniversity of TwenteEnschedeNetherlands

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