Design for Robustness

  • Smita  Krishnaswamy
  • Igor L. Markov
  • John P. Hayes
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 115)

Abstract

We develop several design techniques to improve circuit SER with low area and performance overhead. Our techniques are based on the careful analysis of the interplay between signal probability, observability, and masking mechanisms. The first technique, called SiDeR, involves finding logical implications between signals, using logic simulation signatures to reduce SER. In our second technique, several alternate non-redundant realizations of the same subcircuit are assessed for global SER improvement, and selected based on an objective function that accounts for both SER and area. Our third technique selects gates to harden or replicate by accounting for errors propagating through the gate. Our fourth technique takes advantage of improvements in timing masking, by relocating gates physically to minimize their error-latching windows. The last technique is a form of register retiming that minimizes the probability that soft errors are propagated to a primary output. Our results generally show significant and low-cost improvements in SER.

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Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  • Smita  Krishnaswamy
    • 1
  • Igor L. Markov
    • 2
  • John P. Hayes
    • 2
  1. 1.Department of Biological SciencesColumbia UniversityNew YorkUSA
  2. 2.CSE Division, Department of EECSUniversity of MichiganAnn ArborUSA

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