Chip Planning

  • Andrew B. Kahng
  • Jens Lienig
  • Igor L. Markov
  • Jin Hu


Chip planning deals with large modules such as caches, embedded memories, and intellectual property (IP) cores that have known areas, fixed or changeable shapes, and possibly fixed locations. When modules are not clearly specified, chip planning relies on netlist partitioning (Chap. 2) to identify such modules in large designs. Assigning shapes and locations to circuit modules during chip planning produces blocks, and enables early estimates of interconnect length, circuit delay and chip performance. Such early analysis can identify modules that need improvement. Chip planning consists of three major stages (1) floorplanning, (2) pin assignment, and (3) power planning.


Shape Function Corner Point Hamiltonian Path Sequence Pair Constraint Graph 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Andrew B. Kahng
    • 1
  • Jens Lienig
    • 2
  • Igor L. Markov
    • 3
  • Jin Hu
    • 3
  1. 1.Departments of CSE and ECEUniversity of California at San DiegoLa JollaUSA
  2. 2.Electrical Engineering and Information TechnologyDresden University of TechnologyDresdenGermany
  3. 3.Electrical Engineering and Computer ScienceUniversity of MichiganAnn ArborUSA

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