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Abstract

The primary task of synthesis approaches is to generate circuits that realize the desired functions. Secondarily, it should be ensured that the resulting circuits are as compact as possible. However, the results obtained by synthesis approaches often are sub-optimal. Consequently, in common design flows optimization approaches are applied after synthesis. In this chapter, three new optimization approaches are introduced—each with an own focus on a particular cost metric. The first one considers the reduction of the well-established quantum cost (used in quantum circuits) and the transistor cost (used in CMOS implementations), respectively. The second approach considers the line count in a circuit. Finally, an optimization method is introduced which takes so called Nearest Neighbor Cost (NNC) into account.

Keywords

Truth Table Reversible Logic Quantum Circuit Quantum Gate Synthesis Approach 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Institute of Computer ScienceUniversity of BremenBremenGermany

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