An Asymmetrical Register File: The VWR

  • Francky Catthoor
  • Praveen Raghavan
  • Andy Lambrechts
  • Murali Jayapala
  • Angeliki Kritikakou
  • Javed Absar
Chapter

Abstract

This chapter introduces one of the core contributions of the book which helps improve the energy efficiency of the register file. It presents a novel register file/foreground memory organization which is motivated across application, architecture and physical design abstraction layers. It is fully compatible with the energy-efficient scratchpad memory organisation that is proposed to be used for the large data storage in the previous chapter. It motivates across these different abstraction layers why the proposed register file is more efficient. It also shows that the proposed architecture is energy efficient over different DSP benchmarks.

Keywords

Register File Memory Organization Data Level Parallelism Scratchpad Memory Wide Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  • Francky Catthoor
    • 1
  • Praveen Raghavan
    • 1
  • Andy Lambrechts
    • 1
  • Murali Jayapala
    • 1
  • Angeliki Kritikakou
    • 2
  • Javed Absar
    • 3
  1. 1.Interuniversity MicroElectronics Center IMECLeuvenBelgium
  2. 2.VLSI Design LabUniv. PatrasPatrasGreece
  3. 3.Samsung India Software Operations Pvt. LtdBangaloreIndia

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