Advertisement

Reliability issues of NAND Flash memories

  • C. Zambelli
  • A. Chimenton
  • P. Olivo
Chapter

Abstract

The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view.

Keywords

Threshold Voltage Oxide Degradation Read Operation NAND Flash Floating Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    F. Masuoka, M. Momodomi, Y. Iwata and R. Shirota, “New ultra high density EPROM and Flash EPROM cell with NAND structure”, IEEE Tech. Dig., pp. 552–555, 1987.Google Scholar
  2. 2.
    P. Cappelletti, C. Golla, P. Olivo and E. Zanoni, Eds., Flash Memories. Boston, MA: Kluwer, ch. 5, 1999.Google Scholar
  3. 3.
    M. Lenzlinger and E.H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2”, IEDM Tech. Dig., vol. 40, pp. 273–283, 1969.Google Scholar
  4. 4.
    Y. B. Park and D. K. Schroeder, “Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a Flash EEPROM,” IEEE Transactions on Electron Devices, vol. 45, pp. 1361–1368, 1998.CrossRefGoogle Scholar
  5. 5.
    A. Visconti, and R. Bez, “Advanced Flash memory reliability,” IEEE International Conference on Integrated Circuit Design and Technology, pp. 211–218, 2004.Google Scholar
  6. 6.
    J. H. Lee et al., “Using erase self-detrapped effect to eliminate the Flash cell program/erase cycling Vth window close,” Proceedings of the IRPS, pp. 24–29, 1999.Google Scholar
  7. 7.
    J.D. Lee et al., “Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90nm NAND Flash memory”, Proceedings of the IRPS, pp. 497–501, 2003.Google Scholar
  8. 8.
    S. Piyas, “Calculation of the probability of hole injection from polysilicon gate into silicon dioxide in MOS structures under high-field stress”, Solid-State Electronics, vol. 43, pp. 1677–1687, 1999.CrossRefGoogle Scholar
  9. 9.
    M. V. Fischetti, “Model for the generation of positive charge at the Si-SiO2 interface based on hot-hole injection from the anode”, Physical Review B, vol. 31, pp. 2099–2113, 1985.CrossRefGoogle Scholar
  10. 10.
    D. Ielmini, A.S. Spinelli and A.L. Lacaita, “Recent developments on Flash memory reliability”, Microelectronic Engineering, 14th biennial Conference on Insulating Films on Semiconductors, vol. 80, pp. 321–328, 2005.Google Scholar
  11. 11.
    N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Qingru Meng, N. Righos, Jie Wu, “Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling”, IEEE Transactions on Device and Materials Reliability, vol. 4, pp. 335–344, 2004.CrossRefGoogle Scholar
  12. 12.
    P. Cappelletti, R. Bez, A. Modelli and A. Visconti, “What we have learned on Flash memory reliability in the last ten years”, IEEE Tech. Dig. IEDM, 2004.Google Scholar
  13. 13.
    Chimenton, P. Pellati, and P. Olivo, “Erratic bits in Flash Memories under Fowler-Nordheim Programming,” Japan Journal of Applied Physics, vol. 42, pp. 2041–2043, 2003.CrossRefGoogle Scholar
  14. 14.
    A.S. Spinelli, IRPS tutorial, 2009.Google Scholar
  15. 15.
    Chimenton, P. Pellati, and P. Olivo, “Overerase Phenomena: An Insight Into Flash Memory Reliability,” Proceedings of the IEEE, vol. 91, pp. 617–626, 2003.CrossRefGoogle Scholar
  16. 16.
    “Impact of high tunneling electric fields on erasing instabilities in NOR Flash memories”, IEEE Transactions on Electron Devices, vol. 53, pp. 97–102, 2006.CrossRefGoogle Scholar
  17. 17.
    R. Micheloni, M. Picca, S. Amato, H. Schwalm, M. Scheppler and S. Commodaro, “Non-volatile memories for removable media,” Proceedings of the IEEE, vol. 97, pp. 148–160, 2009.CrossRefGoogle Scholar
  18. 18.
    R. Micheloni, A. Marelli, and R. Ravasio, Error Correction Codes for Non-Volatile Memories, Springer-Verlag, 2008.Google Scholar
  19. 19.
    K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits”, Proceedings of the IEEE, vol. 91, pp. 305–327, 2003.CrossRefGoogle Scholar
  20. 20.
    L. Lopez, P. Masson, D. Nèe and R. Bouchakour, “Temperature and drain voltage dependance of gate-induced drain leakage”, Elsevier Microelectronics Engineering, vol. 72, pp. 101–105, 2004.CrossRefGoogle Scholar
  21. 21.
    Lee Jae-Duk et al., “A new programming disturbance phenomenon in NAND Flash memory by source/drain hot-electrons generated by GIDL current”, IEEE NVSMW, pp. 31–33, 2006.Google Scholar
  22. 22.
    K. Kanda et al., “A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology”, IEEE ISSCC, pp. 430–625, 2008.Google Scholar
  23. 23.
    F. Rahmoune and D. Bauza, “Si-SiO2 interface trap capture properties”, Microelectronic Engineering, vol. 59, pp. 115–118, 2001.CrossRefGoogle Scholar
  24. 24.
    H. Kurata et al., “Random telegraph signal in Flash memory: Its impact on scaling of multilevel Flash memory beyond the 90-nm node”, IEEE Journal of Solid-State Circuits, vol. 42, pp. 1362–1369, 2007.CrossRefGoogle Scholar
  25. 25.
    G. Servalli et al., “A 65 nm NOR Flash technology with 0.042 µm2 cell size for high performance multilevel application", IEEE IEDM Tech. Dig., pp. 869–872, 2005.Google Scholar
  26. 26.
    C.M. Compagnoni, A.S. Spinelli, S. Beltrami, M. Bonanomi and A. Visconti, “Cycling Effect on the Random Telegraph Noise Instabilities of NOR and NAND Flash Arrays”, IEEE Electron Device Letters, vol. 29, pp. 941–943, 2008.CrossRefGoogle Scholar
  27. 27.
    A statistical model of erratic erase based on an automated random telegraph signal characterization technique”, Proceedings of the IRPS, pp. 896–901, 2009.Google Scholar
  28. 28.
    K. Yano et al., “Single-electron memory for giga-to-tera bit storage”, Proceedings of the IEEE, vol. 87, pp. 633–651, 1999.CrossRefGoogle Scholar
  29. 29.
    G. Molas et al., “Impact of few electron phenomena on floating-gate memory reliability”, Electron Devices Meeting, 2004. IEEE IEDM Tech. Dig., pp. 877–880, 2004.Google Scholar
  30. 30.
    C.M. Compagnoni, R. Gusmeroli, A.S. Spinelli and A. Visconti, “Analytical model for the electron-injection statistics during programming of nanoscale NAND Flash memories”, IEEE Transactions on Electron Devices, vol. 55, pp. 3192–3199, 2008.CrossRefGoogle Scholar
  31. 31.
    Constant charge erasing scheme for flash memories”, IEEE Transactions on Electron Devices, vol. 49, pp. 613–618, 2002.CrossRefGoogle Scholar
  32. 32.
    S. Mahapatra, P. B. Kumar, and M. A. Alam, “Investigation and modeling of interface and bulk trap generation during negative bias temperature instability in p-MOSFETs”, IEEE Transactions on Electron Devices, vol. 51, pp. 1371–1379, 2004.CrossRefGoogle Scholar
  33. 33.
    Seung Hwan Seo et al., "Dynamic bias temperature instability-like behaviors under Fowler-Nordheim program/erase stress in nanoscale silicon-oxide-nitride-oxide-silicon memories", Applied Physical Letters, vol. 92, 133508, 2008.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Dip. Ing., Università degli Studi di FerraraFerraraItaly

Personalised recommendations