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NAND overview: from memory to systems

  • R. Micheloni
  • A. Marelli
  • S. Commodaro
Chapter

Abstract

It was in 1965, just after the invention of the bipolar transistor by W. Shockley, W. Brattain and J. Bardeen, that Gordon Moore, co-founder of Intel, observed that the number of transistors per square centimeter in a microchip doubled every year. Moore thought that such trend would have proven true for the years to come as well, and indeed in the following years the density of active components in an integrated circuit kept on doubling every 18 months. For example, in the 18 months that elapsed between the Pentium processor 1.3 and the Pentium-4, the number of transistors grew from 28 to 55 million.

Keywords

Flash Memory Read Operation Memory Controller NAND Flash Flash Translation Layer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    G. Campardo, R. Micheloni, D. Novosel, “VLSI-Design of Non-Volatile Memories”, Springer-Verlag, 2005.Google Scholar
  2. 2.
    R. H. Fowler and L. Nordheim, “Electron Emission in Intense Electric Fields,” Proceedings of the Royal Society of London, Vol. 119, No. 781, May 1928, pp. 173–181.Google Scholar
  3. 3.
  4. 4.
  5. 5.
  6. 6.
    A. Kawaguchi, S. Nishioka, and H. Motoda. “A Flash-Memory Based File System”, Proceedings of the USENIX Winter Technical Conference, pp. 155–164, 1995.Google Scholar
  7. 7.
    J. Kim, J. M. Kim, S. Noh, S. L. Min, and Y. Cho. “A Space-Efficient Flash Translation Layer for CompactFlash Systems,” IEEE Transactions on Consumer Electronics, Vol. 48, No. 2, May 2002, pp.366–375.Google Scholar
  8. 8.
    S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S.-W. Park, and H.-J. Songe. “FAST: A Log-Buffer Based FTL Scheme with Fully Associative Sector Translation”, 2005 US-Korea Conference on Science, Technology, and Entrepreneurship, August 2005.Google Scholar
  9. 9.
    T. Tanzawa, T. Tanaka, K. Takekuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takekuchi, and K. Ohuchi, “A Compact On-Chip ECC for Low Cost Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 32, May 1997, pp. 662–669.CrossRefGoogle Scholar
  10. 10.
    G. Campardo, R. Micheloni et al.,“40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash memory,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, Nov. 2000, pp. 1655–1667.Google Scholar
  11. 11.
    R. Micheloni et al., “A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 142–143, Feb. 2006.Google Scholar
  12. 12.
    R. Micheloni, A. Marelli, R. Ravasio, “Error Correction Codes for Non-Volatile Memories”, Springer-Verlag, 2008.Google Scholar
  13. 13.
    C. Park et al., “A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)”, IEEE Non-Volatile Semiconductor Memory Workshop NVSMW, pp. 17–20, Feb. 2006.Google Scholar
  14. 14.
    D. Nobunaga et al., “A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 426–427, Feb. 2008.Google Scholar
  15. 15.
    K. Kanda et al., “A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology”, in IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 430–431, Feb. 2008.Google Scholar
  16. 16.
    Chang Gyu Hwang, “New Paradigms in the Silicon Industry, International Electron Device Meeting (IEDM), 2006, pp. 1–8.Google Scholar
  17. 17.
    M. Kawano et al., “A 3D Packaging Technology for a 4Gbit Stacked DRAM with 3Gbps Data Transfer, International Electron Device Meeting (IEDM), 2006, pp. 1–4.Google Scholar
  18. 18.
    M. Motoyoshi, “Through-Silicon Via (TSV)”, Proceedings of the IEEE, Vol. 97, Jan. 2009, pp. 43–48.Google Scholar
  19. 19.
    M. Koyanagi et al., “High-Density Through Silicon Vias for 3-D LSIs”, Proceedings of the IEEE, Vol. 97, Jan. 2009, pp. 49–59.Google Scholar
  20. 20.
    G. Campardo, M. Iaculo, F. Tiziani (Eds.), “Memory Mass Storage”, Chap. 6, Springer, 2010.Google Scholar
  21. 21.
    S.-M. Jung, J. Jang, W. Cho et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” IEDM Dig. Tech. Papers, pp. 37–40, Dec. 2006.Google Scholar
  22. 22.
    K. T. Park et al.,” A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 510–511, Feb. 2008.Google Scholar
  23. 23.
    H. Tanaka, M. Kido, K. Yahashi et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Flash Memory,” Dig. Symp. VLSI Technology, pp. 14–15, June 2006.Google Scholar
  24. 24.
    R. Katsumata et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 136–137.Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Integrated Device TechnologyAgrate BrianzaItaly
  2. 2.Pegasus MicroDesignAgrate BrianzaItaly

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