• Yongquan Fan
  • Zeljko Zilic


This chapter brings out the motivation for our research, together with the rudimentary background information on high-speed serial interface standards. The chapter then enumerates the challenges that we are facing in high-speed serial interface testing, validation and debugging, and finally outlines our solutions to some of the most pressing challenges.


Phase Lock Loop Automatic Test Equipment Jitter Performance Random Jitter Jitter Tolerance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [4]
    Y. Fan, Y. Cai and Z. Zilic, "A High Accuracy, High Throughput Jitter Test Solution on ATE for 3 Gbps and 6 Gbps Serial-ATA," Proceedings of IEEE International Test Conference, Oct. 2007Google Scholar
  2. [6]
    Y. Fan and Z. Zilic, “Bit Error Rate Testing of Communication Interfaces,” IEEE Transactions on Instrumentation and Measurements, Vol. 57, No. 5, pp. 897-906, May 2008CrossRefGoogle Scholar
  3. [15]
    P. Noel, F. Zarkeshvari and T. Kwasniewski, “Recent Advances in High-Speed Serial I/O Trends, Standards and Techniques,” Proceedings of 18th Canadian Conference on Electrical and Computer Engineering, 2005Google Scholar
  4. [13]
    Texas Instruments Incorporated
  5. [5]
    Y. Fan and Z. Zilic, "A Versatile Scheme for Validation, Testing and Debugging of High Speed Serail Interfaces," Proceedings of IEEE High Level Design Validation and Test Workshop, HLDVT’09, Nov. 2009Google Scholar
  6. [12]
    Xilinx, Inc. Introducing Virtex-6 and Spartan-6 FPGA Families,
  7. [18]
    T. Miyazaki, M. Hashimoto and H. Onodera, “A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL,” IEICE Transactions on Electronics 2005 E88-C (3): 437-444CrossRefGoogle Scholar
  8. [9]
    IEEE 802.3 Ethernet Working Group.
  9. [8]
    ITRS. The International Technology Roadmap for Semiconductors, 2007 EditionGoogle Scholar
  10. [16]
    H. Johnson and M. Graham, High-Speed Signal Propagation Advanced Black Magic, Prentice Hall PTR, 2003Google Scholar
  11. [3]
    Y. Fan and Z. Zilic "Accelerating Jitter Tolerance Qualification for High Speed Serial Interfaces," Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED'09, March. 2009Google Scholar
  12. [19]
    Altera Corporation, Innovating with a Full Spectrum of 40-nm FPGAs and ASICs with Transceivers, white paperGoogle Scholar
  13. [1]
    Y. Fan and Z. Zilic, "Qualifying Serial Interface Jitter Rapidly and Cost-effectively," Springer Journal of Electronic Testing: Theory and Applications, Volume 26, 2010, 17 pages, DOI: 10.1007/s10836-009-5131-5Google Scholar
  14. [2]
    Y. Fan, Y. Cai, L. Fang, A. Verma, B. Burcanowski, Z. Zilic and S. Kumar, “An Accelerated Jitter Tolerance Test Technique on ATE for 1.5GG/s and 3 GB/s Serial-ATA,” Proceedings of IEEE International Test Conference, Oct. 2006Google Scholar
  15. [10]
    Altera Corporation. Mercury Programmable Logic Device Family Data Sheet, San Jose, California, January 2003Google Scholar
  16. [20]
    M. P. Li, Jitter, Noise, and Signal Integrity at High-Speed, Prentice Hall, 2007Google Scholar
  17. [17]
    A. Hajimiri and T. H. Lee, The Design of Low Noise Oscillators, Kluwer Academic Publishers, 1999Google Scholar
  18. [22]
    Serial ATA International Organization: Serial ATA Revision 3.0. Gold Revision, June 2, 2009Google Scholar
  19. [11]
    Altera Corporation. Stratix IV Device Datasheet, December 2008
  20. [14]
    Cisco Systems Inc.

Copyright information

© Springer Science+Business media B.V. 2011

Authors and Affiliations

  1. 1.High Performance Analog, Texas InstrumentsDallasUSA
  2. 2.Department of Electrical & Computer EngineeringMcGill UniversityMontréalCanada

Personalised recommendations