Abstract
This chapter discusses the design of a 60 GHz Low Noise Amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on Coplanar Waveguide (CPW) modeling, we describe how it’s possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip passive devices. A short description of the transistor model is also provided. Finally, we discuss the details of the LNA design and show how the simulation results compare to the measurements.
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References
F. Gianesello et al., State of the art integrated millimeter wave passive components and circuits in advanced thin SOI CMOS technology on high resistivity substrate. IEEE SOI Conference Proceedings (Oct. 2005) pp 52–53
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Acknowledgments
AcknowledgementThe authors wish to acknowledge ST microelectronics for circuit fabrication and MC2 technologies for measurement support.
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Siligaris, A., Mounet, C., Reig, B., Vincent, P., Michel, A. (2010). CMOS SOI Technology for WPAN: Application to 60 GHZ LNA. In: Amara, A., Ea, T., Belleville, M. (eds) Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol 66. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9379-0_9
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DOI: https://doi.org/10.1007/978-90-481-9379-0_9
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