Analysis of SI Substrate Damage Induced by Inductively Coupled Plasma Reactor with Various Superposed Bias Frequencies

  • Y. Nakakubo
  • A. Matsuda
  • M. Kamei
  • H. Ohta
  • K. Eriguchi
  • K. Ono
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 66)


Plasma-induced Si substrate damage has become one of the critical issues in advanced MOSFETs with shallower junction in source/drain (S/D) extension regions, since the damaged layer thickness will be in conflict with the device design margin such as junction depth [1]. This Si substrate damage is realized as “Si recess” [2] as shown in Fig. 1. Although Si recess is considered to induce dopant loss and performance degradation in MOSFETs, few attentions has been paid to suppress Si recess from the viewpoint of plasma design. Moreover, one can easily observe a constant thickness of Si recess in ultra-scaled MOSFETs recently presented at many conferences [3–5]. It is worthy to note that the thickness is considered to be governed by plasma parameters such as ion energy distribution function (IEDF), electron temperature and plasma density [6]. In order to understand the mechanism and to control the damage, the plasma-induced defects in Si surface layer should be quantitatively estimated, and then, plasma designs should be optimized. Defect generation probability was proposed from an optical analysis as a measure of the damage [7], on one hand. With regard to plasma design, on the other, a plasma source driven by the superimposed dual bias frequency was reported in order to control an IEDF [8] and believed to be a promising candidate for future plasma processes. Recently the effects of superposed bias-frequency on the defect generation probability have been preliminary reported [9]. In this paper, the effect of bias power with the superposed configurations on defect generation process will be investigated in detail from various aspects. The structure of interfacial damaged layer (IL) will be analyzed by spectroscopic ellipsometry and photoreflectance spectroscopy. Also for the purpose of verifying the above methods and clarifying the interfacial growth and carrier trap site generation in the vicinity of plasma-exposed surface, the result by a capacitance–voltage (C–V) measurement (electrical test) will be discussed.


Spectroscopic Ellipsometry Bias Power Surface Layer Thickness Silicon Substrate Surface Plasma Design 
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Acknowledgement We thank Drs. M. Yoshimaru, M. Nakamura, H. Nakagawa, S. Noda and K. Ishikawa at Semiconductor Technology Academic Research Center (STARC) for their helpful discussion. This work was financially supported in part by STARC.


  1. 1.
    K. Eriguchi, K. Takahashi, K. Ono, Plasma-induced damage and its impacts on the reliability of advanced semiconductor devices, Proceedings of the 6th International Conference Reactive Plasmas and 23rd Symposium Plasma Processing, 2006, pp. 5–6Google Scholar
  2. 2.
    T. Ohchi et al., Reducing damage to Si substrate during gate etching processes, Proceedings of the Symposium on Dry Process, 2007, pp. 285–286Google Scholar
  3. 3.
    W.-H. Lee et al., High performance 65nmSOI Technology with enhanced transistor strain and advanced-low-K BEOL, IEDM Technical Digest, 2005, pp. 61–65Google Scholar
  4. 4.
    A. Steegen et al., 65nm CMOS technology for low power applications, IEDM Technical Digest, 2005, pp. 69–72Google Scholar
  5. 5.
    S.A. Vitale, B.A. Smith, Reduction of silicon recess caused by plasma oxidation during high-density plasma polysilicon gate etching. J. Vaccum Sci. Technol. B21, 2205–2211 (2003)CrossRefGoogle Scholar
  6. 6.
    M.A. Lieberman, A.J. Lichtenberg, Principles of Plasma Discharges and Materials Processing, 2nd edn. (Wiley-Interscience, New York, 2005)CrossRefGoogle Scholar
  7. 7.
    K. Eriguchi, K. Ono, Quantitative and comparative characterizations of plasma process-induced damage in advanced metal -oxide-semiconductor devices. J. Phys. D Appl. Phys. 41, 024002 (2008)CrossRefGoogle Scholar
  8. 8.
    A. Kojima et al., Dual frequency superimposed (DFS) rf capacitive coupled plasma etch process, Proceedings of the Symposium on Dry Process, 2003, pp. 13–17Google Scholar
  9. 9.
    Y. Nakakubo et al., Scaling of plasma-induced defect generation probability in Si: Effects of bias voltage at single- and superposed-frequencies, Proceedings of the Symposium on Dry Process, 2007, pp. 287–288Google Scholar
  10. 10.
    A. Matsuda, Y. Nakakubo, Y. Ueda, H. Ohta, K. Eriguchi, K. Ono, Significance of interface layer between surface layer and Si substrate in plasma-exposed structures and its impacts on plasma-induced damage analysis, Ext. Abs. Solid State Dev. Mat., 2008, pp. 358–359Google Scholar
  11. 11.
    D.E. Aspnes, Optical properties of thin films. Thin Solid Films 89, 249–262 (1982)CrossRefGoogle Scholar
  12. 12.
    D.E. Aspnes, Third-derivative modulation spectroscopy with low-field electroreflectance. Surf. Sci. 37, 418–442 (1973)CrossRefGoogle Scholar
  13. 13.
    J.T. Fitch, C.H. Bjorkman, G. Lucovsky, F.H. Pollak, X. Yin, Intrinsic stress and stress gradients at the SiO2/Si interface in structures prepared by thermal oxidation of Si and subjected to rapid thermal annealing. J. Vac. Sci. Technol. A7, 775–781 (1989)CrossRefGoogle Scholar
  14. 14.
    H. Shen, M. Dutta, Franz–Keldysh oscillations in modulation spectroscopy. J. Appl. Phys. 78, 2151–2176 (1995)CrossRefGoogle Scholar
  15. 15.
    F.H. Pollak, H. Shen, Modulation spectroscopy of semiconductors: bulk/thin film, microstructures, surfaces/interfaces and devices. Mater. Sci. Eng. R 10, 275–374 (1993)CrossRefGoogle Scholar
  16. 16.
    S.M. Sze, Physics of Semiconductor Devices, 2nd edn. (Wiley-Interscience, New York, 1981)Google Scholar
  17. 17.
    A. Kubota, D.J. Economou, A molecular dynamics simulation of ultrathin oxide films silicon: Growth by thermal O atoms and sputtering by 100 eV Ar+ ions. IEEE Trans. Plasma Sci. 27, 1416–1425 (1999)CrossRefGoogle Scholar
  18. 18.
    Y. Osano, M. Mori, N. Itabashi, K. Takahashi, K. Eriguchi, K. Ono, A model analysis of feature profile evolution and microscopic uniformity during polysilicon gate etching in Cl2/O2 plasmas. Jpn. J. Appl. Phys. 45, 8157–8162 (2006)CrossRefGoogle Scholar
  19. 19.
    H. Wada, M. Agata, K. Eriguchi, A. Fujimoto, T. Kanashima, M. Okuyama, Photoreflectance characterization of the plasma-induced damage in Si substrate. J. Appl. Phys. 88, 2336–2337 (2000)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  • Y. Nakakubo
    • 1
  • A. Matsuda
    • 1
  • M. Kamei
    • 1
  • H. Ohta
    • 1
  • K. Eriguchi
    • 1
  • K. Ono
    • 1
  1. 1.Graduate School of EngineeringKyoto UniversityKyotoJapan

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