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Metal Gate Effects on a 32 nm Metal Gate Resistor

  • Thuy Dao
  • Ik_Sung Lim
  • Larry Connell
  • Dina H. Triyoso
  • Youngbog Park
  • Charlie Mackenzie
Chapter
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 66)

Abstract

At the 32 nm technology node, the change from a P+ polysilicon / SiON gate stack to a P+ A-silicon/metal gate/high-K dielectric will have a significant impact on RF passives, especially the MOSCAPs and gate resistors.

Keywords

Atomic Layer Deposition Complementary Metal Oxide Semiconductor Flicker Noise Negative Temperature Coefficient Positive Temperature Coefficient 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgement This work has been supported by the Bulk CMOS technology development project at the IBM Microelectronics, Div. Semiconductor Research & Development Center, Hopewell Junction, NY 12533.

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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  • Thuy Dao
    • 1
  • Ik_Sung Lim
    • 2
  • Larry Connell
    • 3
  • Dina H. Triyoso
    • 1
  • Youngbog Park
    • 2
  • Charlie Mackenzie
    • 2
  1. 1.Freescale SemiconductorAustinUSA
  2. 2.Freescale SemiconductorTempeUSA
  3. 3.Freescale SemiconductorLake ZurichUSA

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