Independent-Double-Gate FINFET SRAM Cell for Drastic Leakage Current Reduction
The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling . Short channel effects (SCEs) such as threshold voltage (V th ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.
KeywordsLeakage Current Control Gate SRAM Cell CMOS Inverter Drain Induce Barrier Lowering
Acknowledgement The author would like to thank Ms. Yuki Ishikawa, Dr. Yongxun Liu, Dr. Takashi Matsukawa, Dr. Shin-ichi O’uch, Dr. Meishoku Masahara, Mr. Junichi Tsukada, Mr. Kenichi Ishii, Ms. Hiromi Yamauchi, and Dr. Eiichi Suzuki for their support and helpful discussions.This work was supported in part by the Innovation Research Project on Nanoelectronics Materials and Structures t from the METI.
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