How Does Inverse Temperature Dependence Affect Timing Sign-Off

Abstract

As processing technology migrates into sub-90 nm region, design performance can be affected by factors that were considered secondary before. One of such factors is the Inversed Temperature Dependence (ITD) effect [1]. When a circuit is operating in low voltage, the propagation delay of a cell may decrease as the temperature increases [4]. The reason behind ITD effect is due to the temperature effect on the threshold voltage, V_TH. As supply voltage (V_DD ) scaled, the value of |V_GS – V_TH|, the absolute difference between transistor gate to source voltage and threshold voltage, decreases. The smaller |V_GS – V_TH| makes saturation current more sensitive to change in V_TH, which decreases as the increase of temperature. The smaller V_TH incurs more current that makes the device switching faster. On the other hand, transition delay is also proportional to the electron mobility, which decreases as the temperature rises. Hence the device performance depends on the racing condition of electron mobility and V_TH together as temperature rises. Traditionally, timing is signed off at two extreme temperature corners, one representing the best case and the other representing the worst case. With ITD, the highest sign-off temperature can no longer guarantee the worst case, and vice versa. This poses a serious problem to the timing sign-off methodology, i.e. it is possible that the worst-case temperature occurs at some intermediate point and finding this point can be quite difficult. Due to the goal of having low power design, modern designs are implemented by standard cells with high V_TH extensively. Coupling with the ITD effect, it is necessary to understand the impact on sign-off methodology.