Abstract
Today’s System-on-a-Chip (SoC) designs are becoming more and more complex. This creates demand for system level Computer-Aided-Design (CAD) tools that allow early hardware and software co-development, hardware and software performance evaluation and fast system-level modeling. The latest achievements in this area are mostly due to wide SystemC adoption and the recent introduction of the TLM 2.0 standard. The complexity of today’s SoC designs makes High-Level Synthesis (HLS) an important part of modern design flows.In this paper, we analyze two basic approaches to HLS user input that exist today – sequential ANSI C/C++ and SystemC Synthesizable Subset. Based upon the results of our analysis, we propose a new concept – SystemC Synthesizable Superset – a solution that combines advantages of both approaches (ANSI C/C++ and SystemC), but does not inherit their disadvantages. Our HLS-oriented concept features a predefined library of HLS modules, user threads with implicit timing specification and a set of TLM 2.0 compatible interfaces. In addition, our HLS objects allow for various levels of simulation abstraction (or timing accuracy), such as cycle-accurate at transaction boundaries (CATB), approximately-timed and loosely-timed modeling. Simulation abstraction levels can be switched without the need to rewrite the user system specification that determines high flexibility level of our solution. In conclusion, we demonstrate a simple synthesizable video system and compare the simulation speeds at different abstraction levels.
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References
R.A. Bergamaschi, S. Raje, Observable time windows: verifying high-level synthesis results. Design Test Comput. IEEE 14(2), 40–50 (1997). URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=587740&isnumber=12899
L.P. Carloni, K.L. McMillan, A. Saldanha, A.L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design. Comput. Aided Design 309–315 (1999). 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=810667&isnumber=17544
J. Cornet, F. Maraninchi, L. Maillet-Contoz, A method for the efficient development of timed and untimed transaction-level models of systems- on-chip. Design, Automation and Test in Europe, 2008. DATE ’08, pp. 9–14, 10–14 March 2008. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4484652&isnumber=4484624
E. Grimpe, F. Oppenheimer, Object-oriented high level synthesis based on SystemC. Electronics, Circuits and Systems, 2001. ICECS 2001.The 8th IEEE International Conference, 1, 529–534 (2001). URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=957798&isnumber=20704
E. Grimpe, F. Oppenheimer, Extending the SystemC synthesis subset by object-oriented features. Hardware/Software Codesign and System Synthesis, 2003. First IEEE/ACM/IFIP International Conference, pp. 25–30, 1–3 Oct. 2003. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1275251&isnumber=28532
IEEE Std 1666TM-2005, IEEE Standard SystemC Ⓡ Language Reference Manual, http://standards.ieee.org
B. Niemann, C. Haubelt, Formalizing TLM with communicating state machines, in Proceedings of Forum on Specification and Design Languages 2006 (FDL 2006), pp. 285–292, 2006. URL: http://www.scientificcommons.org/21338913
Open SystemC Initiative (OSCI), http://www.systemc.org
Open SystemC Initiative (OSCI) OSCI TLM-2.0 User Manual, 2007–2008, http://www.systemc.org; http://ieeexploreieee.org/stamp/stamp.jsp?arnumber=810667&isnumber=17544
K. Pakalniškis, E. Kazanavičius, Concepts of high level synthesis using SystemC, ISSN 1392–2114 ULTRAGARSAS, Nr.2 (43). 2002
S. Pasricha, N. Dutt, M. Ben-Romdhane, Extending the transaction level modeling approach for fast communication architecture exploration. Design Automation Conference, 2004. Proceedings 41st, pp. 113–118, 2004. URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1322453&isnumber=29281
Working Group of Open SystemC Initiative (OSCI), SystemC Synthesizable Subset, Draft 1.1.18, 2004, http://www.systemc.org
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Smirnov, M., Takach, A. (2010). A SystemC Superset for High-Level Synthesis. In: Borrione, D. (eds) Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s. Lecture Notes in Electrical Engineering, vol 63. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9304-2_8
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DOI: https://doi.org/10.1007/978-90-481-9304-2_8
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