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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 63))

Abstract

The context of this chapter is the dynamic assertion-based verification (ABV) of TLM SystemC models. We have developed a methodology for checking temporal properties during the SystemC simulation. The assertions are expressed in the PSL language, including the possibility to use its modeling layer, and the method supports timed as well as untimed TLM descriptions. It is implemented in a prototype tool called ISIS. We describe its principles and technical characteristics, and we report various experimental results.

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Notes

  1. 1.

    This work is partly supported by the French projects SFINCS (ANR) and SoCKET (FCE).

  2. 2.

    The grammar given in the PSL reference manual only specifies that a verification unit can contain HDL declarations and statements as well as assertions. In order to avoid any confusion during parsing, we have chosen special keywords to introduce declarations and statements.

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Correspondence to Luca Ferro .

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Ferro, L., Pierre, L. (2010). ISIS: Runtime Verification of TLM Platforms. In: Borrione, D. (eds) Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s. Lecture Notes in Electrical Engineering, vol 63. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9304-2_13

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  • DOI: https://doi.org/10.1007/978-90-481-9304-2_13

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