Advertisement

Benchmark Tests for MOSFET Compact Models

  • Xin Li
  • Weimin Wu
  • Gennady Gildenblat
  • Colin C. McAndrew
  • Andries J. Scholten

Abstract

It has long been recognized that, apart from computational efficiency and accuracy of fitting experimental data, compact MOS transistor models should exhibit qualitatively correct physical behavior for drain current, terminal charges, noise, and all derivatives. Physics-based models may automatically embody the correct physical behavior for long-channel devices, but compact models of scaled transistors inevitably involve approximations that can introduce unphysical qualitative characteristics. Over time, several “benchmark tests” were developed to ensure that transistor characteristics predicted by a compact model satisfy the needs of the circuit designers, especially for analog and mixed-signal design. As the importance of RF CMOS circuits increases, the requirements for qualitatively correct physical behavior of compact MOSFET models are becoming more stringent (for example, it is now common to require the existence of fifth order derivatives) and several new benchmark tests, targeted for RF design needs, were developed. This chapter describes both traditional and newly developed MOSFET model benchmark tests and applies them to the PSP model.

Keywords

Benchmark Test Gate Bias Strong Inversion Asymmetric Model Inversion Region 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Bendix, P., Rakers, P., Wagh, P., Lemaitre, L., Grabinski, W., McAndrew, C.C., Gu, X., Gildenblat, G.: RF distortion analysis with compact MOSFET models. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 9–12 (2004) Google Scholar
  2. 2.
    Bressoud, D.M.: A Radical Approach to Real Analysis. The Mathematical Association of America (2007) Google Scholar
  3. 3.
    Brews, J.R.: A charge-sheet model of the MOSFET. Solid-State Electron. 21(2), 345–355 (1978) CrossRefGoogle Scholar
  4. 4.
    Chen, Q., Wu, Z.Y., Su, R., Goo, J.S., Thuruthiyil, C., Radwin, M., Subba, N., Suryagandh, S., Ly, T., Wason, V., An, J., Icel, A.: Extraction of self-heating free I-V curves including the substrate current of PD SOI MOSFETs. In: Proc. IEEE Int. Conf. on Microelectron. Test Structures, pp. 272–275 (2007) Google Scholar
  5. 5.
    Chen, T.L., Gildenblat, G.: Symmetric bulk charge linearisation in charge-sheet MOSFET model. Electron. Lett. 37(12), 791–793 (2001) CrossRefGoogle Scholar
  6. 6.
    Gildenblat, G., Wang, H., Chen, T.L., Gu, X., Cai, X.: SP: an advanced surface-potential-based compact MOSFET model. IEEE J. Solid-State Circuits 39(9), 1394–1406 (2004) CrossRefGoogle Scholar
  7. 7.
    Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: An advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53(9), 1979–1993 (2006) CrossRefGoogle Scholar
  8. 8.
    Gildenblat, G., Zhu, Z., McAndrew, C.C.: Surface potential equation for bulk MOSFET. Solid-State Electron. 53(1), 11–13 (2009) CrossRefGoogle Scholar
  9. 9.
    Jin, X., Ou, J.J., Chen, C.H., Liu, W., Deen, M.J., Gray, P.R., Hu, C.: An effective gate resistance model for CMOS RF and noise modeling. In: IEDM Tech. Dig., pp. 961–964 (1998) Google Scholar
  10. 10.
    Jindal, R.P.: Effect of induced gate noise at zero drain bias in field-effect transistors. IEEE Trans. Electron Devices 52(3), 432–434 (2005) CrossRefGoogle Scholar
  11. 11.
    Joardar, K., Gullapalli, K.K., McAndrew, C.C., Burnham, M.E., Wild, A.: An improved MOSFET model for circuit simulation. IEEE Trans. Electron Devices 45(1), 134–148 (1998) CrossRefGoogle Scholar
  12. 12.
    Klaassen, D.B.M., van Langevelde, R., Scholten, A.J.: Compact CMOS modelling for advanced analogue and RF applications. IEICE Trans. Electron. E87-C(6), 854–866 (2004) Google Scholar
  13. 13.
    Lee, T.H.: The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn. Cambridge University Press, Cambridge (2004) Google Scholar
  14. 14.
    Li, X., Wu, W., Jha, A., Gildenblat, G., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., McAndrew, C.C., Watts, J., Olsen, M., Coram, G., Chaudhry, S., Victory, J.: Benchmarking the PSP compact model for MOS transistors. In: Proc. IEEE Int. Conf. on Microelectron. Test Structures, pp. 259–264 (2007) Google Scholar
  15. 15.
    Li, X., Wu, W., Jha, A., Gildenblat, G., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., McAndrew, C.C., Watts, J., Olsen, C.M., Coram, G.J., Chaudhry, S., Victory, J.: Benchmark tests for MOSFET compact models with application to the PSP model. IEEE Trans. Electron Devices 56(2), 243–251 (2009) CrossRefGoogle Scholar
  16. 16.
    Liu, W.: MOSFET Models for SPICE Simulation: Including BSIM3V3 and BSIM. Wiley-Interscience, New York (2001) Google Scholar
  17. 17.
    McAndrew, C.C.: Practical modeling for circuit simulation. IEEE J. Solid-State Circuits 33(3), 439–448 (1998) CrossRefGoogle Scholar
  18. 18.
    McAndrew, C.C.: Useful numerical techniques for compact modeling. In: Proc. IEEE Int. Conf. on Microelectron. Test Structures, pp. 121–126 (2002) Google Scholar
  19. 19.
    McAndrew, C.C.: Validation of MOSFET model source–drain symmetry. IEEE Trans. Electron Devices 53(9), 2202–2206 (2006) CrossRefGoogle Scholar
  20. 20.
    McAndrew, C.C., Gummel, H.K., Singhal, K.: Benchmarks for compact MOSFET models. In: SEMATECH Compact Models Workshop (1995) Google Scholar
  21. 21.
    Pao, H.C., Sah, C.T.: Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electron. 9(10), 927–937 (1966) CrossRefGoogle Scholar
  22. 22.
    Paasschens, J.C.J., Scholten, A.J., van Langevelde, R.: Generalizations of the Klaassen-Prins equation for calculating the noise of semiconductor device. IEEE Trans. Electron Devices 52(11), 2463–2472 (2005) CrossRefGoogle Scholar
  23. 23.
    Scheinberg, N., Pinkhasov, A.: A computer simulation model for simulating distortion in FET resistors. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 19(9), 981–989 (2000) CrossRefGoogle Scholar
  24. 24.
    Scholten, A.J., Tiemeijer, L.F., van Langevelde, R., Havens, R.J., Zegers-van Duijnhoven, A.T.A., Venezia, V.C.: Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices 50, 618–632 (2003) CrossRefGoogle Scholar
  25. 25.
    Scholten, A.J., van Langevelde, R., Tiemeijer, L.F., Klaassen, D.B.M.: Compact modeling of noise in CMOS. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 711–716 (2006) Google Scholar
  26. 26.
    Scholten, A.J., Smit, G.D.J., De Vries, B.A., Tiemeijer, L.F., Croon, J.A., Klaassen, D.B.M., van Langevelde, R., Li, X., Wu, W., Gildenblat, G.: The new CMC standard compact MOS model PSP: Advantages for RF applications. IEEE J. Solid-State Circuits 44(5), 1415–1424 (2009) CrossRefGoogle Scholar
  27. 27.
    Su, L., Chung, J., Antoniadis, D., Goodson, K., Flik, M.: Measurement and modeling of self-heating in SOI nMOSFET’s. IEEE Trans. Electron Devices 41(1), 69–75 (1994) CrossRefGoogle Scholar
  28. 28.
    Su, P., Fung, S., Tang, S., Assaderaghi, F., Hu, C.: BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 197–200 (2000) Google Scholar
  29. 29.
    Tenbroek, B., Lee, M., Redman-White, W., Bunyan, R., Uren, M.: Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE J. Solid-State Circuits 33(7), 1037–1046 (1998) CrossRefGoogle Scholar
  30. 30.
    Trofimenkoff, F.: Field-dependent mobility analysis of the field-effect transistor. Proc. IEEE 53(11), 1765–1766 (1965) CrossRefGoogle Scholar
  31. 31.
    Tsividis, Y.: Problems with precision modeling of analog MOS LSI. In: IEDM Tech. Dig., vol. 28, pp. 274–277 (1982) Google Scholar
  32. 32.
    Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. McGraw-Hill, New York (1999) Google Scholar
  33. 33.
    Tsividis, Y., Masetti, G.: Problems in precision modeling of the MOS transistor for analog applications. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 3(1), 72–79 (1984) CrossRefGoogle Scholar
  34. 34.
    Tsividis, Y.P., Suyama, K.: MOSFET modeling for analog circuit CAD: problems and prospects. IEEE J. Solid-State Circuits 29(3), 210–216 (1994) CrossRefGoogle Scholar
  35. 35.
    van der Ziel, A.: Noise in Solid State Devices and Circuits. Wiley-Interscience, New York (1986) Google Scholar
  36. 36.
    van Langevelde, R., Scholten, A.J., Havens, R.J., Tiemeijer, L.F., Klaassen, D.B.M.: Advanced compact MOS modelling. In: Proc. Eur. Solid-State Device Res. Conf., pp. 81–88 (2001) Google Scholar
  37. 37.
    van Langevelde, R., Scholten, A.J., Klaassen, D.B.M.: Physical background of MOS model 11. Nat.Lab. Unclassified Report, NL-TN 2003/00239 (2003). http://www.nxp.com/models/mos_models/model11/
  38. 38.
    Victory, J., Yan, Z., Gildenblat, G., McAndrew, C.C., Zheng, J.: A physically based, scalable MOS varactor model and extraction methodology for RF applications. IEEE Trans. Electron Devices 52(7), 1343–1353 (2005) CrossRefGoogle Scholar
  39. 39.
    Vogelsong, R., Brzezinski, C.: Simulation of thermal effects in electrical systems. In: Proc. IEEE Appl. Power Electron. Conf. and Expos. (APEC), pp. 353–356 (1989) Google Scholar
  40. 40.
    Wang, H., Gildenblat, G.: A robust large signal non-quasi-static MOSFET model for circuit simulation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 5–8 (2004) Google Scholar
  41. 41.
    Wang, H., Chen, T.L., Gildenblat, G.: Quasi-static and nonquasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges. IEEE Trans. Electron Devices 50(11), 2262–2272 (2003) CrossRefGoogle Scholar
  42. 42.
    Wang, H., Li, X., Wu, W., Gildenblat, G., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: Unified non-quasi-static MOSFET model for large-signal and small-signal simulations. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 823–826 (2005) Google Scholar
  43. 43.
    Wang, H., Li, X., Wu, W., Gildenblat, G., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: A unified nonquasi-static MOSFET model for large-signal and small-signal simulations. IEEE Trans. Electron Devices 53(9), 2035–2043 (2006) CrossRefGoogle Scholar
  44. 44.
    Watts, J., McAndrew, C.C., Enz, C., Galup-Montoro, C., Gildenblat, G., Hu, C., van Langevelde, R., Miura-Mattausch, M., Rios, R., Sah, C.T.: Advanced compact models for MOSFETs. In: Tech. Proc. Workshop on Compact Modeling, pp. 3–12 (2005) Google Scholar
  45. 45.
    Wu, W., Chen, T.L., Gildenblat, G., McAndrew, C.C.: Physics-based mathematical conditioning of the MOSFET surface potential equation. IEEE Trans. Electron Devices 51(7), 1196–1199 (2004) CrossRefGoogle Scholar
  46. 46.
    Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: A compact model for valence-band electron tunneling current in partially depleted SOI MOSFETs. IEEE Trans. Electron Devices 54(2), 316–322 (2007) CrossRefGoogle Scholar
  47. 47.
    Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations. Solid-State Electron. 53(1), 18–29 (2009) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  • Xin Li
    • 1
  • Weimin Wu
    • 1
  • Gennady Gildenblat
    • 1
  • Colin C. McAndrew
    • 2
  • Andries J. Scholten
    • 3
  1. 1.Ira A. Fulton School of Engineering, Department of Electrical EngineeringArizona State UniversityTempeUSA
  2. 2.Freescale SemiconductorTempeUSA
  3. 3.NXP-TSMC Research CenterEindhovenThe Netherlands

Personalised recommendations