Advertisement

PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs

  • Weimin Wu
  • Wei Yao
  • Gennady Gildenblat

Abstract

Surface-potential-based models, which represent the mainstream approach to compact modeling of bulk MOSFETs, are now in the process of being applied to SOI devices. In this chapter we discuss two advanced SOI models—PSP-SOI-PD for partially depleted devices and PSP-SOI-DD including the dynamic depletion effects. Both models are based on the popular PSP model of bulk MOSFETs. The theoretical foundation of all PSP-family models is the symmetric linearization method that allows one to raise the physical contents of the compact model without prohibitive increase in its computational complexity. In addition to the physics-based structure of the new models inherited from bulk PSP, they account for phenomena specific to SOI devices (e.g. floating body, and valence band tunneling current) and include a detailed description of parasitic effects. We discuss both the theoretical developments and verification of the model against test data and TCAD simulations with particular emphasis on the interplay between the model structure and its simulation capabilities.

Keywords

Compact Model Body Resistance Inversion Charge Body Potential TCAD Simulation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The development of PSP-SOI is partially supported by Semiconductor Research Corporation. The authors are grateful to C.C. McAndrew, J. Watts, and G.O. Workman for insightful discussions, and H. Barnaby and G. Dessai for reading the manuscript and valuable comments.

References

  1. 1.
    Anil, K.G., Mahapatra, S., Eisele, I.: Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs. In: IEDM Tech. Dig., pp. 675–678 (2000) Google Scholar
  2. 2.
    Bolouki, S., Maddah, M., Afzali-Kusha, A., El Nokali, M.: A unified IV model for PD/FD SOI MOSFETs with a compact model for floating body effects. Solid-State Electron. 47(11), 1909–1915 (2003) CrossRefGoogle Scholar
  3. 3.
    Brews, J.R.: A charge-sheet model of the MOSFET. Solid-State Electron. 21, 345–355 (1978) CrossRefGoogle Scholar
  4. 4.
    Cai, J., Sah, C.T.: Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors. J. Appl. Phys. 89(4), 2272–2285 (2001) CrossRefGoogle Scholar
  5. 5.
    Chatterjee, P.K., Leiss, J.E., Taylor, G.W.: A dynamic average model for the body effect in ion implanted short channel (L=1 μm) MOSFET’s. IEEE Trans. Electron Devices 28(5), 606–607 (1981) CrossRefGoogle Scholar
  6. 6.
    Chen, T.L., Gildenblat, G.: Symmetric bulk charge linearization of charge-sheet MOSFET model. Electron. Lett. 37(12), 791–793 (2001) CrossRefGoogle Scholar
  7. 7.
    Chen, J., Chan, T.Y., Ko, P.K., Hu, C.: Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. 8, 515–517 (1987) CrossRefGoogle Scholar
  8. 8.
    Chen, Q., Suryagandh, S., Goo, J.S., An, J.X., Thuruthiyil, C., Icel, A.B.: Impact of gate induced drain leakage and impact ionization currents on hysteresis modeling of PD SOI circuits. In: Tech. Proc. Workshop on Compact Modeling, pp. 570–573 (2007) Google Scholar
  9. 9.
    Chen, Q., Wu, Z.Y., Su, R.Y.K., Goo, J.S., Thuruthiyil, C., Radwin, M., Subba, N., Suryagandh, S., Ly, T., Wason, V., An, J.X., Icel, A.B.: Extraction of self-heating free I-V curves including the substrate current of PD SOI MOSFETs. In: IEEE Int. Conf. on Microelectron. Test Structures, pp. 272–275 (2007) Google Scholar
  10. 10.
    Chuang, C.T., Joshi, R.V., Puri, R., Kim, K.: Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits. In: Proc. Int. Symp. on Quality Electron. Des., pp. 153–158 (2003) Google Scholar
  11. 11.
    Chuang, C.T., Puri, R.: Effects of gate-to-body tunneling current on PD/SOI CMOS latches. In: Proc. Int. Conf. Simul. of Semicond. Processes and Devices, pp. 291–294 (2003) Google Scholar
  12. 12.
    Colinge, J.P.: Silicon-On-Insulator Technology: Materials to VLSI, 3rd edn. Springer, Berlin (2004) CrossRefGoogle Scholar
  13. 13.
    Dessai, G., Dey, A., Gildenblat, G., Smit, G.D.J.: Symmetric linearization method for double-gate and surrounding-gate MOSFET models. Solid-State Electron. 53(5), 548–556 (2009) CrossRefGoogle Scholar
  14. 14.
    Dessai, G., Wu, W., Gildenblat, G.: Compact charge model for independent-gate asymmetric DGFET. IEEE Trans. Electron Devices (submitted) Google Scholar
  15. 15.
    Dieudonne, F., Jomaah, J., Balestra, F.: Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs. IEEE Electron Device Lett. 23(12), 737–739 (2002) CrossRefGoogle Scholar
  16. 16.
    Faccio, F., Anghinolfi, F., Heijne, E.H.M., Jarron, P., Cristoloveanu, S.: Noise contribution of the body resistance in partially-depleted SOI MOSFETs. IEEE Trans. Electron Devices 45(5), 1033–1038 (1998) CrossRefGoogle Scholar
  17. 17.
    Fischetti, M.V., Sano, N., Laux, S.E., Natori, K.: Full-band Monte Carlo simulation of high-energy transport and impact ionization of electrons and holes in Ge, Si, and GaAs. In: Proc. Int. Conf. Simul. of Semicond. Processes and Devices, pp. 43–44 (1996) Google Scholar
  18. 18.
    Getreu, I.E.: Modeling the Bipolar Transistor. Tektronix, Beaverton (1976) Google Scholar
  19. 19.
    Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53(9), 1979–1993 (2006) CrossRefGoogle Scholar
  20. 20.
    Gildenblat, G., Wang, H., Chen, T.L., Cai, X.: SP: an advanced surface-potential-based compact MOSFET model. IEEE J. Solid-State Circuits 39(9), 1394–1406 (2004) CrossRefGoogle Scholar
  21. 21.
    Gildenblat, G., Zhu, Z., McAndrew, C.C.: Surface potential equation for bulk MOSFET. Solid-State Electron. 53(1), 11–13 (2009) CrossRefGoogle Scholar
  22. 22.
    Goo, J.S., Williams, R.Q., Workman, G.O., Chen, Q., Lee, S., Nowak, E.J.: Compact modeling and simulation of PD-SOI MOSFETs: current status and challenges. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 265–272 (2008) Google Scholar
  23. 23.
    Gu, X., Wang, H., Chen, T.L., Gildenblat, G.: Substrate current in surface-potential-based compact MOFET models. In: Tech. Proc. Nanotechnol. Conf., pp. 310–313 (2003) Google Scholar
  24. 24.
    Gu, X., Chen, T.L., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Shapira, S., Stiles, K.: A surface potential-based compact model of n-MOSFET gate-tunneling current. IEEE Trans. Electron Devices 51(1), 127–135 (2004) CrossRefGoogle Scholar
  25. 25.
    Gummel, H.K., Poon, H.C.: An integral charge control model of bipolar transistors. Bell Syst. Tech. J. 49(5), 827–852 (1970) Google Scholar
  26. 26.
    Jang, S.L., Huang, B.R., Ju, J.J.: A unified analytical fully depleted and partially depleted SOI MOSFET model. IEEE Trans. Electron Devices 46(9), 1872–1876 (1999) Google Scholar
  27. 27.
    Jin, W., Chan, P.C.H., Fung, S.K.H., Ko, P.K.: Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET’s. IEEE Trans. Electron Devices 46(6), 1180–1185 (1999) CrossRefGoogle Scholar
  28. 28.
    Jin, W., Fung, S.K.H., Liu, W., Chan, P.C.H., Hu, C.: Self-heating characterization for SOI MOSFET based on AC output conductance. In: IEDM Tech. Dig., pp. 175–178 (1999) Google Scholar
  29. 29.
    Joshi, R.V., Chuang, C.T., Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.: Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM. In: Symp. on VLSI Technol. Dig. of Tech. Papers, pp. 75–76 (2001) Google Scholar
  30. 30.
    Kusu, S., Ishimura, K., Ohyama, K., Miyoshi, T., Hori, D., Sadachika, N., Murakami, T., Ando, M., Mattausch, H.J., Miura-Mattausch, M., Baba, S., Ida, J.: Consistent dynamic depletion model of SOI-MOSFETs for device/circuit optimization. In: Proc. IEEE Int. SOI Conf., pp. 59–60 (2008) Google Scholar
  31. 31.
    Lemaitre, L., McAndrew, C.C., Hamm, S.: ADMS: automated device model synthesize. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 27–30 (2002) Google Scholar
  32. 32.
    Lim, H.K., Fossum, J.G.: Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s. IEEE Trans. Electron Devices 30(10), 1244–1251 (1983) CrossRefGoogle Scholar
  33. 33.
    Lu, P.F., Chuang, C.T., Ji, J., Wagner, L.F., Hsieh, C.M., Kuang, J.B., Hsu, L.L.C., Pelella, M.M., Chu, S.F.S. Jr., Anderson, C.J.: Floating-body effects in partially depleted SOI CMOS circuits. IEEE J. Solid-State Circuits 32(8), 1241–1253 (1997) CrossRefGoogle Scholar
  34. 34.
    Mallikarjun, C., Bhat, K.: Numerical and charge sheet models for thin-film SOI MOSFETs. IEEE Trans. Electron Devices 37(9), 2039–2051 (1990) CrossRefGoogle Scholar
  35. 35.
    McAndrew, C.C.: Practical modeling for circuit simulation. IEEE J. Solid-State Circuits 33(3), 439–448 (1998) CrossRefGoogle Scholar
  36. 36.
    McAndrew, C.C., Victory, J.J.: Accuracy of approximations in MOSFET charge models. IEEE Trans. Electron Devices 49(1), 72–81 (2002) CrossRefGoogle Scholar
  37. 37.
    Mercha, A., Rafi, J.M., Simoen, E., Augendre, E., Claeys, C.: “Linear kink effect” induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs. IEEE Trans. Electron Devices 50(7), 1675–1682 (2003) CrossRefGoogle Scholar
  38. 38.
    Murakami, T., Ando, M., Sadachika, N., Yoshida, T., Miura-Mattausch, M.: Modeling of floating-body effect in silicon-on-insulator metal-oxide-silicon field-effect transistor with complete surface-potential-based description. Jpn. J. Appl. Phys. 47(4), 2556–2559 Google Scholar
  39. 39.
    Nakayama, H., Su, P., Hu, C., Nakamura, H., Komatsu, H., Takeshita, K., Komatsu, Y.: Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 381–384 (2001) Google Scholar
  40. 40.
    Ortiz-Conde, A., Garcia Sanchez, F.J., Schmidt, P.E., Sa-Neto, A.: The nonequilibrium inversion layer charge of the thin-film SOI MOSFET. IEEE Trans. Electron Devices 36(9), 1651–1656 (1989) CrossRefGoogle Scholar
  41. 41.
    Pao, H.C., Sah, C.T.: Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electron. 9, 927–937 (1966) CrossRefGoogle Scholar
  42. 42.
    PSP group: PSP Manual Version 102.2 (2007). http://pspmodel.asu.edu/downloads/psp1022_summary.pdf
  43. 43.
    Sadachika, N., Kitamaru, D., Uetsuji, Y., Navarro, D., Yusoff, M.M., Ezaki, T., Mattausch, H.J., Miura-Mattausch, M.: Completely surface-potential-based compact model of the fully depleted SOI-MOSFET including short-channel effects. IEEE Trans. Electron Devices 53(9), 2017–2024 (2006) CrossRefGoogle Scholar
  44. 44.
    Scholten, A.J., Tiemeijer, L.F., van Langevelde, R., Havens, R.J., Zegers-van Duijnhoven, A.T.A., Venezia, V.C.: Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices 50(3), 618–632 (2003) CrossRefGoogle Scholar
  45. 45.
    Scholten, A.J., Smit, G.D.J., Durand, M., van Langevelde, R., Klaassen, D.B.M.: The physical background of JUNCAP2. IEEE Trans. Electron Devices 53(9), 2098–2107 (2006) CrossRefGoogle Scholar
  46. 46.
    Shahidi, G.G., Ajmera, A., Assaderaghi, F., Bolam, R.J., Hovel, H., Leobandung, E., Rausch, W., Sadana, D., Schepis, D., Wagner, L.F., Wissel, L., Wu, K., Davari, B.: Device and circuit design issues in SOI technology. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 339–346 (1999) Google Scholar
  47. 47.
    Simoen, E., Mercha, A., Claeys, C., Lukyanchikova, N.B., Garhar, N.: Electron valence band tunnelling induced excess Lorentzian noise in fully depleted SOI transistors. In: Proc. Eur. Solid-State Device Res. Conf., pp. 279–282 (2003) Google Scholar
  48. 48.
    Sinitsky, D., Fung, S., Tang, S., Su, P., Chan, M., Ko, P., Hu, C.: A dynamic depletion SOI MOSFET model for SPICE. In: Symp. on VLSI Technol. Dig. of Tech. Papers, pp. 114–115 (1998) Google Scholar
  49. 49.
    Sleight, J., Rios, R.: A continuous compact MOSFET model for fully- and partially-depleted SOI devices. IEEE Trans. Electron Devices 45(4), 821–825 (1998) CrossRefGoogle Scholar
  50. 50.
    Smit, G.D.J., Scholten, A.J., Serra, N., Pijper, R.M.T., van Langevelde, R., Mercha, A., Gildenblat, G., Klaassen, D.B.M.: PSP-based compact FinFET model describing dc and RF measurements. In: IEDM Tech. Dig., pp. 1–4 (2006) Google Scholar
  51. 51.
    Su, L.T., Chung, J.E., Antoniadis, A.D., Goodson, K.E., Flik, M.I.: Measurement and modeling of self-heating in SOI nMOSFET’s. IEEE Trans. Electron Devices 41(1), 69–75 (1994) CrossRefGoogle Scholar
  52. 52.
    Su, P., Fung, S.K.H., Assaderaghi, F., Hu, C.: A body-contact SOI MOSFET model for circuit simulation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 50–51 (1999) Google Scholar
  53. 53.
    Su, P., Fung, S.K.H., Tang, S., Assaderaghi, F., Hu, C.: BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 197–200 (2000) Google Scholar
  54. 54.
    Su, P., Goto, K., Sugii, T., Hu, C.: Enhanced substrate current in SOI MOSFETs. IEEE Electron Device Lett. 23(5), 282–284 (2002) CrossRefGoogle Scholar
  55. 55.
    Su, P., Fung, S.K.H., Wyatt, P.W., Wan, H., Chan, M., Niknejad, A.M., Hu, C.: A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 241–244 (2003) Google Scholar
  56. 56.
    Tenbroek, B.M., Lee, M.S.L., Redman-White, W., Bunyan, R.J.T., Uren, M.J.: Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE J. Solid-State Circuits 33(7), 1037–1046 (1998) CrossRefGoogle Scholar
  57. 57.
    Tseng, Y.C., Huang, W.M., Mendicino, M., Monk, D.J., Welch, P.J., Woo, J.C.S.: Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs. IEEE Trans. Electron Devices 48(7), 1428–1437 (2001) CrossRefGoogle Scholar
  58. 58.
    Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. McGraw-Hill, New York (1999) Google Scholar
  59. 59.
    Tsu, R., Esaki, L.: Tunneling in a finite superlattice. Appl. Phys. Lett. 22(11), 562–564 (1973) CrossRefGoogle Scholar
  60. 60.
    van Langevelde, R., Scholten, A.J., Klaassen, D.B.M.: MOS Model 11, Level 1102 (2004). http://www.nxp.com/models/mos_models/
  61. 61.
    Victory, J., Zhu, Z., Zhou, Q., Wu, W., Gildenblat, G., Yan, Z., Cordovez, J., McAndrew, C.C., Anderson, F., Paassches, J.C.J., van Langevelde, R., Kolev, P., Cherne, R., Yao, C.: PSP-based scalable MOS varactor model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 495–502 (2007) Google Scholar
  62. 62.
    Vogelsong, R., Brzezinski, C.: Simulation of thermal effects in electrical systems. In: IEEE Appl. Power Electron. Conf. and Expos. (APEC), pp. 353–356 (1989) Google Scholar
  63. 63.
    Wan, H., Xi, X., Niknejad, A., Hu, C.: BSIMSOI4.0 MOSFET Model. University of California, Berkeley, CA (2005) Google Scholar
  64. 64.
    Wang, H., Chen, T.L., Gildenblat, G.: Quasi-static and non-quasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges. IEEE Trans. Electron Devices 50(11), 2262–2272 (2003) CrossRefGoogle Scholar
  65. 65.
    Ward, D.E., Dutton, R.W.: A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits 13, 703–708 (1978) CrossRefGoogle Scholar
  66. 66.
    Workman, G.O., Fossum, J.G.: A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance. IEEE Trans. Electron Devices 45(10), 2138–2145 (1998) CrossRefGoogle Scholar
  67. 67.
    Workman, G.O., Fossum, J.G.: Physical noise modeling of SOI MOSFETs with analysis of the Lorentzian component in the low-frequency noise spectrum. IEEE Trans. Electron Devices 47(6), 1192–1201 (2000) CrossRefGoogle Scholar
  68. 68.
    Wu, W., Chen, T.L., Gildenblat, G., McAndrew, C.C.: Physics-based mathematical conditioning of the MOSFET surface potential equation. IEEE Trans. Electron Devices 51(7), 1196–1199 (2004) CrossRefGoogle Scholar
  69. 69.
    Wu, W., Li, X., Wang, H., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C.: SP-SOI: a third generation surface potential based compact SOI MOSFET model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 819–822 (2005) Google Scholar
  70. 70.
    Wu, W., Li, X., Gildenblat, G., Workman, G., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: a surface potential based compact model of partially depleted SOI MOSFETs (invited). In: Proc. IEEE Custom Integr. Circuits Conf., pp. 41–48 (2007) Google Scholar
  71. 71.
    Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Watts, J.: A nonlinear body resistance model for accurate PD/SOI technology characterization. In: Proc. IEEE Int. SOI Conf., pp. 151–152 (2008) Google Scholar
  72. 72.
    Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations. Solid-State Electron. 53, 18–29 (2009) CrossRefGoogle Scholar
  73. 73.
    Wu, W., Yao, W., Gildenblat, G.: Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs. Solid-State Electron (2010). doi: 10.1016/j.sse.2009.12.040 Google Scholar
  74. 74.
    Yang, J.W., Fossum, J.G., Workman, G.O., Huang, C.L.: A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits. Solid-State Electron. 48(2), 259–270 (2004) CrossRefGoogle Scholar
  75. 75.
    Yu, Y., Kim, S., Hwang, S., Ahn, D.: All-analytic surface potential model for SOI MOSFETs. IEE Proc. Circuits Device Syst. 152(2), 183–188 (2005) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.School of Electrical, Computer, and Energy EngineeringArizona State UniversityTempeUSA

Personalised recommendations