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Introduction

  • Antonio Carlos Schneider Beck Fl.
  • Luigi Carro
Chapter

Abstract

This introductory chapter presents several challenges that architectures are facing these days, such as the imminent end of the Moore’s law as it is known today; the usage of future technologies that will replace silicon; the stagnation of ILP increase in superscalar processors and their excessive power consumption and, most importantly, how the aforementioned aspects are impacting on the development of new architectural alternatives. All these aspects point to the fact that new architectural solutions are necessary. Then, the main reasons that motivated the writing of this book are shown. Several aspects are discussed, as the why ILP does not increase as before; the use of both combinational logic and reconfigurable fabric to speedup execution of data dependent instructions; the importance of maintaining binary compatibility, which is the possibility of reusing previously compiled code without any kind of modification; yield issues and the costs of fabrication. This chapter ends with a brief review of what will be seen in the rest of the book.

Keywords

Pipeline Stage Combinational Logic Branch Prediction ASIC Design Branch Predictor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Austin, T., Blaauw, D., Mahlke, S., Mudge, T., Chakrabarti, C., Wolf, W.: Mobile supercomputers. Computer 37(5), 81–83 (2004). doi: 10.1109/MC.2004.1297253 CrossRefGoogle Scholar
  2. 2.
    Burger, D., Goodman, J.R.: Billion-transistor architectures: There and back again. Computer 37(3), 22–28 (2004). doi: 10.1109/MC.2004.1273999 CrossRefGoogle Scholar
  3. 3.
    Burns, J., Gaudiot, J.L.: Smt layout overhead and scalability. IEEE Trans. Parallel Distrib. Syst. 13(2), 142–155 (2002). doi: 10.1109/71.983942 CrossRefGoogle Scholar
  4. 4.
    Conte, G., Tommesani, S., Zanichelli, F.: The long and winding road to high-performance image processing with mmx/sse. In: CAMP’00: Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP’00), p. 302. IEEE Computer Society, Los Alamitos (2000) CrossRefGoogle Scholar
  5. 5.
    Flynn, M.J., Hung, P.: Microprocessor design issues: Thoughts on the road ahead. IEEE Micro 25(3), 16–31 (2005). doi: 10.1109/MM.2005.56 CrossRefGoogle Scholar
  6. 6.
    Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 4th edn. Morgan Kaufmann, San Mateo (2006) zbMATHGoogle Scholar
  7. 7.
    Kim, N.S., Austin, T., Blaauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V.: Leakage current: Moore’s law meets static power. Computer 36(12), 68–75 (2003). doi: 10.1109/MC.2003.1250885 CrossRefGoogle Scholar
  8. 8.
    Koufaty, D., Marr, D.T.: Hyperthreading technology in the netburst microarchitecture. IEEE Micro 23(2), 56–65 (2003) CrossRefGoogle Scholar
  9. 9.
    McLellan, E.J., Webb, D.A.: The alpha 21264 microprocessor architecture. In: ICCD’98: Proceedings of the International Conference on Computer Design, p. 90. IEEE Computer Society, Los Alamitos (1998) Google Scholar
  10. 10.
    Prakash, T.K., Peng, L.: Performance characterization of spec cpu2006 benchmarks on Intel core 2 duo processor. ISAST Trans. Comput. Softw. Eng. 2(1), 36–41 (2008) Google Scholar
  11. 11.
    Rutenbar, R.A., Baron, M., Daniel, T., Jayaraman, R., Or-Bach, Z., Rose, J., Sechen, C.: (when) will fpgas kill asics? (panel session). In: DAC’01: Proceedings of the 38th Annual Design Automation Conference, pp. 321–322. ACM, New York (2001). doi: 10.1145/378239.378499 Google Scholar
  12. 12.
    Semiconductors, T.I.T.R.: Itrs 2008 edition. Tech. Rep., ITRS (2008). http://www.itrs.net
  13. 13.
    Sima, D.: Decisive aspects in the evolution of microprocessors. Proc. IEEE 92(12), 1896–1926 (2004) CrossRefGoogle Scholar
  14. 14.
    Thompson, S., Parthasarathy, S.: Moore’s law: The future of si microelectronics. Mater. Today 9(6), 20–25 (2006) CrossRefGoogle Scholar
  15. 15.
    Thompson, S.E., Chau, R.S., Ghani, T., Mistry, K., Tyagi, S., Bohr, M.T.: In search of “forever,” continued transistor scaling one new material at a time. IEEE Trans. Semicond. Manuf. 18(1), 26–36 (2005). doi: 10.1109/TSM.2004.841816 CrossRefGoogle Scholar
  16. 16.
    Vahid, F.: The softening of hardware. Computer 36(4), 27–34 (2003). doi: 10.1109/MC.2003.1193225 CrossRefGoogle Scholar
  17. 17.
    Vahid, F.: It’s time to stop calling circuits “hardware”. Computer 40(9), 106–108 (2007). doi: 10.1109/MC.2007.322 CrossRefGoogle Scholar
  18. 18.
    Vahid, F., Lysecky, R.L., Zhang, C., Stitt, G.: Highly configurable platforms for embedded computing systems. Microelectron. J. 34(11), 1025–1029 (2003) CrossRefGoogle Scholar
  19. 19.
    Wall, D.W.: Limits of instruction-level parallelism. In: ASPLOS-IV: Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 176–188. ACM, New York (1991). doi: 10.1145/106972.106991 CrossRefGoogle Scholar
  20. 20.
    Wilcox, K., Manne, S.: Alpha processors: A history of power issues and a look to the future. In: Proceedings of the Cool-Chips Tutorial. Held in Conjunction with the International Symposium on Microarchitecture. ACM/IEEE, New York (1999) Google Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  • Antonio Carlos Schneider Beck Fl.
    • 1
  • Luigi Carro
    • 1
  1. 1.Instituto de InformáticaUniversidade Federal do Rio Grande do Sul (UFRGS)Porto AlegreBrazil

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