Summary and Conclusions
Today, the design and verification of electronic systems is a very challenging task. To cope with the steadily increasing complexity and the pressure of time to-market the design entry has been lifted to high-level descriptions, i.e. the level of abstraction for designing systems has been raised. In this book a prominent design flow based on the system description language SystemC was considered. However, while the single-language concept of the SystemC design flow allows a continuous modeling from system level down to synthesizable descriptions, only low verification quality is achieved. There are two main reasons: First, the existing verification techniques are decoupled and are often based on simple simulation techniques. Second, the resulting verification quality in terms of the covered functionality is not ensured automatically along the refinement process. Therefore, a quality-driven design and verification flow was developed in this book. The “traditional” SystemC design flow is enhanced by 1. Dedicated verification techniques which target each level of abstraction and employ formal methods where possible and 2. Complementing each verification task by measuring the resulting quality.
In the new flow three levels of abstraction for modeling of digital systems are distinguished: The system-level model that is refined to the synthesizable top level model which again consists of several block-level models.