Block-Level Verification

Abstract

In this chapter techniques for verification at the block level are presented. Figure 4.1 shows the respective parts of the proposed design and verification flow that are described in this chapter. The motivation for considering components of the system at the block level before addressing the top level in more detail is as follows. Based on the SystemC design methodology the system is stepwise refined and finally consists of hierarchical modules (with the respective functionality) and interfaces for communication. At this point all parts of the system are synthesizable. But from the verification perspective along the refinement process until reaching the synthesizable descriptions only simulation based techniques have been used to check that the specification is met. Even with the strong constraint-based simulation methods and the complementing testbench quality check as presented in Chapter 3 typically not all design errors can be found. Thus, in the following formal methods are applied to the blocks of the design. Thereby, their functional correctness can be guaranteed.

The middle of Figure 4.1 shows the proposed verification techniques as well as the corresponding quality check for the block level. First, in this chapter a property checking approach for SystemC is presented. The approach uses the front-end of [FGC⁺04], which is part of the SystemC design environment SyCE¹ [DFGG05], to generate a Finite State Machine (FSM) representation from a SystemC description.