FlexPath NP—Flexible, Dynamically Reconfigurable Processing Paths in Network Processors

Abstract

This chapter presents the results of the FlexPath network processor (NP) project. Based on observations on current NP implementations and relevant Internet traffic scenarios, a new NP architecture is defined that makes use of reconfigurable packet processing paths in order to improve the system performance. We propose to extend state-of-the-art processor-centric NP architectures with specific hardware units in order to classify the incoming traffic into separate processing classes. For each traffic class, we can provide an optimized processing path, i.e. a functional unit traversal sequence within the NP. In addition, we propose to offload significant shares of the traffic to a dedicated hardware path in order to bypass the CPU cluster and save precious programmable processing resources. We also address the problem of multi-processor load balancing in the context of multi-core network processors. The concepts have been evaluated on an analytical and simulative level, and finally a demonstrator has been implemented on an FPGA in order to prove the claimed performance advantage by measurements.