MORPHEUS accelerators programs are process compositions working on local memories. They produce instruction level parallelism and concurrent memory accesses. Spatial design is a middleware between high level compilers and circuits mapped on the accelerators. Its core is a model for process code used by high level development tools and for synthesis on heterogeneous targets. The framework also ensures system performance by overlapping communications and computations.
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Lagadec, L., Picard, D., Pottier, B. (2009). Spatial Design. In: Voros, N.S., Rosti, A., Hübner, M. (eds) Dynamic System Reconfiguration in Heterogeneous Platforms. Lecture Notes in Electrical Engineering, vol 40. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-2427-5_13
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DOI: https://doi.org/10.1007/978-90-481-2427-5_13
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