Guaranteeing the correctness of a manufactured circuit is an important task in industrial chip design flow. To ensure that the circuit functions correctly, test patterns are applied. The problem of generating test patterns for the postproduction test was considered in this book. Basic concepts and classical algorithms for Automatic Test Pattern Generation (ATPG) have been reviewed. Furthermore, the problem of Boolean Satisfiability (SAT) has been introduced and the basic algorithms and techniques have been explained. Due to recent advances in SAT solving, modern SAT solvers have been applied successfully in various problem domains, e.g. verification and design debugging. How to generate test patterns for the Stuck-At Fault Model (SAFM) using a SAT instance such that the ATPG process benefits from the powerful Boolean reasoning embedded in modern SAT solvers has been considered. This basic approach and several improvements to create the SAT-based ATPG engine PASSAT have been described during the subsequent chapters.
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© 2009 Springer-Verlag Berlin Heidelberg
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(2009). Summary and Outlook. In: Test Pattern Generation using Boolean Proof Engines. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-2360-5_11
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DOI: https://doi.org/10.1007/978-90-481-2360-5_11
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-2359-9
Online ISBN: 978-90-481-2360-5
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