Abstract
This chapter discusses about the constraining design using Synopsys DC compiler. Every ASIC design needs to meet the constraints. The constraints are classified as optimization, design rule, and environmental constraints. This chapter covers the area minimization techniques, design optimization techniques using the meaningful practical design scenarios. Even this chapter describes about the key important commands used to boost the design performance. This chapter even discusses about the commands used for the FSM extractions. The sample scripts are given in the chapter and can be used for the design optimization and the report generations.
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www.synpsys.com Design compiler® user guide version D-2010.03-SP2, June 2010
User guide version D-2010.03, March 2010
www.synpsys.com Guidelines and practices for successful logic synthesis version 1998.08, August 1998
www.synopsys.com Synopsys timing constraints and optimization
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© 2016 Springer India
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Taraate, V. (2016). Constraining ASIC Design. In: Digital Logic Design Using Verilog. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2791-5_12
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DOI: https://doi.org/10.1007/978-81-322-2791-5_12
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Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2789-2
Online ISBN: 978-81-322-2791-5
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