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Designing of DPA Resistant Circuit Using Secure Differential Logic Gates

  • Palavlasa ManojEmail author
  • Datti Venkata Ramana
Conference paper
  • 863 Downloads
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 410)

Abstract

Crypto circuits can be attacked using the technique of differential power analysis by another/separate party, using power consumption dependence on secret message/information for extracting the critical data (information). To avoid DPA (Differential Power Analysis) and security bases, differential logic styles are basically used, because of constant power dissipation. This paper proposes a new design methodology using OR-NOR gates in 90 nm VLSI technology using SABL (Sense Amplifier Based Logic) for DPDN (Differential Pull down Logic) to secure/protect differential logic gates and to eliminate charge in the pull-down differential gate and to remove the memory effect.

Keywords

Sense amplifier based logic Differential Power Analysis Differential Pull Down Network Universal logic gates 90 nm VLSI technology 

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Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringGMR Institute of TechnologyRajamIndia

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