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Design of Optimized Multiply Accumulate Unit Using EMBR Techniques for Low Power Applications

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Computational Intelligence in Data Mining—Volume 2

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 411))

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Abstract

Composite operations of arithmetic are extensively used in the applications of Digital Signal Processing (DSP). An optimized Multiply Accumulator Unit using fused Add-Multiply (FAM) operator by exploring structured and proficient recoding methods utilizing them. This paper deals with the study of performance comparisons of 16-bit and 32-bit MAC design based on EMBR techniques in terms of look up tables and power utilization with 8-bit and 16-bit recoding form of Modified Booth (MB) multiplier.

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References

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Authors and Affiliations

  1. Department of ECE, GMR Institute of Technology, Rajam, India

    K. N. Narendra Swamy & J. Venkata Suman

Authors
  1. K. N. Narendra Swamy
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  2. J. Venkata Suman
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Correspondence to K. N. Narendra Swamy .

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Editors and Affiliations

  1. Department of Computer Science Engineering and Information Technology, Veer Surendra Sai University of Technology, Sambalpur, Odisha, India

    Himansu Sekhar Behera

  2. Department of Computer Science and Engineering, National Institute of Technology, Rourkela, India

    Durga Prasad Mohapatra

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Narendra Swamy, K.N., Venkata Suman, J. (2016). Design of Optimized Multiply Accumulate Unit Using EMBR Techniques for Low Power Applications. In: Behera, H., Mohapatra, D. (eds) Computational Intelligence in Data Mining—Volume 2. Advances in Intelligent Systems and Computing, vol 411. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2731-1_29

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  • DOI: https://doi.org/10.1007/978-81-322-2731-1_29

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  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-2729-8

  • Online ISBN: 978-81-322-2731-1

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