Design of CMOS Ring Oscillators with Low Phase Noise and Power Dissipation for Data Transmission in RF Range

Abstract

This paper presents designing and comparative analysis of noise and power for ring voltage-controlled oscillator (VCO) architectures. A two-stage complementary metal–oxide–semiconductor (CMOS) ring VCO and differential ring oscillator are designed with 180 nm technology and 3.3 V supply for high-resolution and low phase noise. The relative parameters that influence the VCO phase noise are discussed and analysed comprehensively. The tuning range of the designed VCO is from 1 to 5 GHz for a five-stage circuit and 1−2 GHz for a two-stage circuit. An improved VCO unit circuit is obtained by adding a wave shaping circuit at the output of VCO. We have taken the upper frequency range as 5 GHz because it will work properly for a data rate of up to 10 Gbps for an evenly phased signal passing with Nyquist data rate. Our simulation result proves that the designed two-stage CMOS differential VCO has low noise in comparison to other architectures. The circuit can also provide higher stability, better gain and dissipate low power. Our designed VCO is a relaxation oscillator and it will form triangular waveform in the high speed frequency range. The value obtained for phase noise for the two-stage differential CMOS ring oscillator is −292.52 dBc/Hz. Cadence Virtuoso has been used for simulation purpose.