An FPGA-Based Embedded System for Real-Time Data Processing
An embedded architecture for high-speed data acquisition and display system is proposed for continuous data monitoring in real-time. In addition to this, a coherent averaging block is added as an IP core which average out the random noise of any signal under process. An analog to digital converter (ADC) AD9265 having maximum sampling speed of 125 MSPS is interfaced with the embedded system to digitize the signal. The entire embedded system has been implemented on FPGA using VIRTEX-II PRO device. The experimental results of the proposed work are flashed on the front panel of the LCD in real-time.
KeywordsCoherent averaging Embedded system Field programmable gate arrays (FPGAs) Random noise
The author wishes to thank Department of Information Technology, Govt. of India, New Delhi for their support through project.
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