A Low-Power High-Speed Double Manchester Carry Chain with Carry-Skip Using D3L

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 381)


In this paper, multi-output domino 8-bit Manchester carry chain with carry-skip capability using data-driven logic is proposed. In this, two parallel carry chains compute even and odd carries independently and the carry-skip capability is applied to the odd carry chain. The dynamic power consumption is reduced using the data-driven dynamic logic, where the clock is replaced with data. The circuits are designed and simulated using Cadence Virtuoso tool with CMOS 180 nm TSMC technology. Further, the structures are implemented for 16, 32, and 64-bits. The PDP of 64-bit double Manchester carry chain with skip capability using D3L shows an improvement of 16 % among the reported ones.


Carry look-ahead adder (CLA) Manchester Carry chain (MCC) Multi-output domino Carry-skip logic Data-driven logic (D3L) Power delay product (PDP) 


  1. 1.
    Parhami, B.: Computer Arithmetic, Algorithms and Hardware. Oxford Univ. Press, New York (2000)Google Scholar
  2. 2.
    Weste, N., Harris, D.: CMOS VLSI Design, A Circuit and System Perspective. Addison-Wesley, Reading (2004)Google Scholar
  3. 3.
    Weinberger, A., Smith, J.L.: A logic for high speed addition. Nat. Bureau Stand. Circ. 591, 3–12 (1958)Google Scholar
  4. 4.
    Chan, P.K., Schlag, M.D.F.: Analysis and design of CMOS Manchester adders with variable Carry-skip. IEEE Trans. Comput. 39(8), 983–992 (1990)Google Scholar
  5. 5.
    Wang, Z., Jullien, G., Miller, W., Wang, J., Bizzan, S.: Fast adders using enhanced multiple output domino logic. IEEE J. Solid State Circuits 32(2), 206–214 (1997)Google Scholar
  6. 6.
    Ruiz, G.A.: New static multi-output Carry look-ahead cmos adders. Proc. Inst. Elect. Eng. Circuits Devices Syst. 144(6), 350–354 (1997)Google Scholar
  7. 7.
    Osorio, M., Sampaio, C., Reis, A., Ribas, R.: Enhanced 32-bit Carry look-ahead adder using multiple output enable-disable CMOS differential logic. In: Proceedings of 17th Symposium on Integrated Circuits and System Design, pp. 181–185 (2004)Google Scholar
  8. 8.
    Amin, A.A.: Area-efficient high-speed Carry chain. Electron. Lett. 43(23), 1258–1260 (2007)Google Scholar
  9. 9.
    Efstathiou, C., Owda, Z., Tsiatouhas, Y.: New high speed multioutput carry look-ahead adders. IEEE Trans. Circuits Syst.-II, Express Briefs 60(10), 667–671 (2013)Google Scholar
  10. 10.
    Rafati, W.R., Fakhraie, S.M., Smith, K.C. Low power data-driven dynamic logic (D3L). Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) 752–755 (2000)Google Scholar
  11. 11.
    Purohit, S., Lanuzza, M., Margala, M. :Design space exploration of split-path data driven dynamic full adder. J. Low Power Electron. 6(4), 469–481 (2010)Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.ECE DepartmentAnna UniversityChennaiIndia

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