Abstract
This paper proposes a technique for designing low-leakage stable SRAM cell which can mitigate impact of V t (threshold voltage) variation. The architecture of the proposed transmission gate-based 9-transistor SRAM cell (TG9T) is almost similar to that of 7-transistor SRAM cell (7T) except the access transistors, which are replaced with transmission gates. In this study, various key design metrics like noise margin, leakage current, and hold power are simulated for both cells and compared. The proposed design provides 1.25× lower leakage current and 1.46× higher SINM (static current noise margin) while bearing 3.8× penalty in WTI (write trip current) compared with 7T. Proposed design exhibits its robustness by achieving 1.1× tighter spread in hold power compared to 7T.
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Pal, S., Krishna Madan, Y., Islam, A. (2016). Low-Leakage, Low-Power, High-Stable SRAM Cell Design. In: Satapathy, S., Raju, K., Mandal, J., Bhateja, V. (eds) Proceedings of the Second International Conference on Computer and Communication Technologies. Advances in Intelligent Systems and Computing, vol 379. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2517-1_53
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DOI: https://doi.org/10.1007/978-81-322-2517-1_53
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