Advertisement

Low-Leakage, Low-Power, High-Stable SRAM Cell Design

  • Soumitra Pal
  • Y. Krishna Madan
  • Aminul Islam
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 379)

Abstract

This paper proposes a technique for designing low-leakage stable SRAM cell which can mitigate impact of V t (threshold voltage) variation. The architecture of the proposed transmission gate-based 9-transistor SRAM cell (TG9T) is almost similar to that of 7-transistor SRAM cell (7T) except the access transistors, which are replaced with transmission gates. In this study, various key design metrics like noise margin, leakage current, and hold power are simulated for both cells and compared. The proposed design provides 1.25× lower leakage current and 1.46× higher SINM (static current noise margin) while bearing 3.8× penalty in WTI (write trip current) compared with 7T. Proposed design exhibits its robustness by achieving 1.1× tighter spread in hold power compared to 7T.

Keywords

MOSFET Transmission gate SINM WTI Leakage current Hold power 

References

  1. 1.
    Hennessy, J.L., Patterson, V.: Computer architecture: a quantitative approach, Chap. 5. Morgan Kaufman (2006)Google Scholar
  2. 2.
    Jain, S.K., Agarwal, P.: A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology. In: 2006 19th International Conference VLSI Design, pp. 3–7 Jan 2006Google Scholar
  3. 3.
    Athe, P., Dasgupta, S.: A comparative study of 6T, 8T and 9T Decanano SRAM cell. IEEE Symposium Industrial Electronics and Applications (ISIEA), vol. 2, pp. 889–894 Oct 2009Google Scholar
  4. 4.
    Kim, T.-H., Liu, J., Kim, C.H.: A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode. IEEE J. Solid-State Circuits 44(6), 1785–1795 (2009)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Chang, L., et al.: An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches. IEEE J. Solid-State Circuits 43(4), 956–963 (2008)CrossRefGoogle Scholar
  6. 6.
    Liu, Z., Kursun, V.: Characterization of a novel nine-transistor SRAM cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(4), 488–492 (2008)CrossRefGoogle Scholar
  7. 7.
    Calhoun, B.H., Chandrakasan, A.: A 256-kb sub-threshold SRAM design for ultra-low-voltage operation. IEEE J. Solid-State Circuits 42(3), 680–688 (2007)CrossRefGoogle Scholar
  8. 8.
    Chang, I.J., Kim, J.-J., Park, S.P., Roy, K.: A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. IEEE J. Solid-State Circuits 44(2), 650–658 (2009)CrossRefGoogle Scholar
  9. 9.
    Aly, R.E., Bayoumi, M.A.: Low-power cache design using 7T SRAM Cell. IEEE Trans. Circuits Syst.—II: Express Briefs 54(4) (2007)Google Scholar
  10. 10.
    Vaddi, R., Dasgupta, S., Agarwal, R.P.: Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS. IEEE Trans. Electron Dev. 57, 654–664 (2010)CrossRefGoogle Scholar
  11. 11.
    Seevinck, E., et al.: Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits SC-22(5), 748–754 (1987)CrossRefGoogle Scholar
  12. 12.
    Islam, A., Hasan, M., Arslan, T.: Variation resilient subthreshold SRAM cell design technique. Int. J. Electron. 99(9), 1223–1237 (2012)CrossRefGoogle Scholar
  13. 13.
    Pal, S., Bhattacharya, A., Islam, A.: Comparative study of CMOS- and FinFET-based 10T SRAM Cell in Subthreshold regime. In: IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), pp. 507–511, May 2014Google Scholar
  14. 14.
    Islam, A., Hasan, M.: Leakage characterization of 10T SRAM cell. IEEE Trans. Electron Dev. 59(3), 631–638 (2012)CrossRefGoogle Scholar
  15. 15.
    Islam, A., Hasan, M.: Variability aware low leakage reliable SRAM cell design technique. Microelectron. Reliabil. 52(6) (2012)Google Scholar
  16. 16.
    Wann, C. et al.: SRAM cell design for stability methodology. In: Proceedings IEEE VLSI-TSA, pp. 21–22, Apr 2005Google Scholar
  17. 17.
    Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press, New York (2009)Google Scholar

Copyright information

© Springer India 2016

Authors and Affiliations

  1. 1.Electronics and Communication EngineeringBirla Institute of TechnologyRanchiIndia

Personalised recommendations