Estimation of High Performance 3T DRAM Cell at Nanometer Technology

  • Priyanka KushwahEmail author
  • Nikhil Saxena
  • Saurabh Khandelwal
  • Shyam Akashe
Conference paper
Part of the Springer Proceedings in Physics book series (SPPHY, volume 166)


In this paper the analysis of conventional DRAM logic compatible 3T gain cell has been shown. In this paper 3T dram with semantic design technique is presented. The read and write operation for single bit storage is useful in terms of leakage power, static power dissipation, signal to noise ratio and delay time. The simulation result shows that when a wide range of operating voltage is taken, which is from 0.7 to 1.3 V then it is observed that low voltage operation is suitable for low read access time but the leakage power dissipation increases as increase in the range of operating voltage. The design has been carried out at the 45 nm scale technology on cadence virtuoso simulating tool.


Leakage Power Dynamic Random Access Memory Memory Array Word Line Gain Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Gerik CM, Turi MA, Delgado-Frias JG (2012) FinFET 3T and 3T1D dynamic RAM cell. In: Proceedings of IEEE 55th International Midwest symposium, 454–457Google Scholar
  2. 2.
    Akashe S, Mudgal A, Singh SB (2012) Analysis of power in 3T DRAM and 4T DRAM cell design for different technology. Information and communication technology (WICT) world congress, 18–21Google Scholar
  3. 3.
    Singh L, Somkuwar A (2013) Dynamic random access memory with self-controllable voltage level to reduce low leakage current in VLSI. Int J Eng Res Appl (IJERA) 3:2248–9622Google Scholar
  4. 4.
    Singh L, Somkuwar A (2013) 4T DRAM based on self- controllable voltage level technique for low leakage power in VLSI. Int J Emerg Technol Comput Appl Sci (IJETCAS) 3(3):233–237Google Scholar
  5. 5.
    Borah M, Irwin MJ, Owens RM (1995) Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. In: Proceedings of the 8th international conference, 294–298Google Scholar
  6. 6.
    Kim NS, Austin T, Baauw D, Mudge T, Flautner K, Hu JS, Irwin MJ, Kandemir M, Narayanan V (2003) Leakage current: moore’s law meets static power. IEEE Comput Soc 36(12):68–75 (Papers)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  • Priyanka Kushwah
    • 1
    Email author
  • Nikhil Saxena
    • 1
  • Saurabh Khandelwal
    • 1
  • Shyam Akashe
    • 1
  1. 1.ITMGwaliorIndia

Personalised recommendations