Abstract
Row decoder is used to decode the address locations of memory. In this paper designing and power–delay analysis of 2–4 row decoder based on MOS transistor at channel length of 150 nm have been presented. Value of power supply voltage (V dd) has been varied from 0.4 to 1.2 V to plot the variation of power consumption and delay for decoding the rows. According to simulation delay and power consumption are of the order of 10−11 s and 10−4 W, respectively. Tanner Spice (T-SPICE) software has been used to simulate the design.
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Bhowmik, S., Bari, S. (2015). Design of Row Decoder Circuit for Semiconductor Memory at Low Power and Small Delay Using MOS Transistor at Nano Dimension Channel Length. In: Maharatna, K., Dalapati, G., Banerjee, P., Mallick, A., Mukherjee, M. (eds) Computational Advancement in Communication Circuits and Systems. Lecture Notes in Electrical Engineering, vol 335. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2274-3_43
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DOI: https://doi.org/10.1007/978-81-322-2274-3_43
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