Abstract
This paper presents a novel discrete phase-locked loop (DPLL) based on FPGA. In this DPLL, phase offset of reference sinusoidal signal is followed at the output of NCO with no dead zone (i.e., full phase lock-in-range). All the signals and components used in this DPLL system are realized as discrete digital time components. Hilbert transform is used to generate analytic signal, and then CORDIC algorithm in vector mode is used for instantaneous phase detection. A novel simple algorithm is used to compute the phase offset difference between reference sinusoidal signal and NCO output’s discrete sinusoidal values. Either LUT-based sine wave generator or CORDIC-based sine wave generator is used in NCO. The total system is implemented using Xilinx ISE and compared with existing DPLL block. Also, performance of phase lock time and phase lock-in-range is analyzed.
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Bharani dharan, N., Chinnathambi, M., Rajaram, S. (2015). FPGA Implementation of Novel Discrete Phase-Locked Loop. In: Mandal, D., Kar, R., Das, S., Panigrahi, B. (eds) Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2268-2_24
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DOI: https://doi.org/10.1007/978-81-322-2268-2_24
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