Novel Approach of Multiplier Design Using Ancient Vedic Mathematics

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 340)

Abstract

Multiplication is the fundamental operation in mathematics as well as in the field of engineering. Multiplier is the core part of Digital Signal Processor. In this paper a new approach of multiplier design using the Vedic mathematics has been proposed. The procedure of multiplication using Vedic mathematics is very simple, easy and time saving. The design approach of multiplier by using the popular sutra “Ekanyunena Purvena” of Vedic mathematics is very new and novel. This procedure is successfully presented in this paper. The simple algorithm, flow chart, mathematical expression etc. helps the design to understand easily. The core architecture of the multiplier has been also discussed in this paper. The method discussed in this paper is very helpful for some special type of multiplication, like where the multiplicand is an integer and the multiplier is 9 or array of 9 (for example 9 or 99 or 999 or so on). The less complexity is the most important advantage of this digital design.

Keywords

DSP Vedic mathematics Ekanyunena purvena Multiplier 

References

  1. 1.
    Thapliyal, H., Arbania, H.R.: A time-area-power efficient multiplier and square architecture based on ancient indian vedic mathematics. In: Proceedings of the 2004 International Conference on VLSI (VLSI’04), Las Vegas, Nevada, June 2004, pp. 434–439Google Scholar
  2. 2.
    Jagadguru Swami, Sri Bharati Krisna, Tirthaji Maharaja: Vedic Mathematics or Sixteen Simple Mathematical Formulae From the Veda, Delhi, Motilal Banarsidas, Varanasi, India (1965)Google Scholar
  3. 3.
    Saha, P., et al.: ASIC design of a high speed low power circuit for factorial calculation using ancient vedic mathematics. Microelectron. J. 42, 1343–1352 (2011). doi: 10.1016/j.mejo.2011.09.001 CrossRefGoogle Scholar
  4. 4.
    Saha, P., et al.: Improved matrix multiplier design for high speed signal processing applications. IET Circuits Devices 7 Syst. 8(1), 27–37 (2014)CrossRefGoogle Scholar
  5. 5.
    Meheta, P., Gawali, D.: Conventional versus vedic mathematical method for hardware implementation of a multiplier. In: Proceedings of IEEE International Conferences on Advances in Computing, Control and Telecommunication, pp. 640–642, Trivandrum, Kerala (2009)Google Scholar
  6. 6.
    Poornima, M., et al.: Implementation of multiplier using Vedic algorithm. IJITEE 2(6), 219–223 (2013) Google Scholar
  7. 7.
    Jeganathan Sriskandarajah: Secrets of ancient maths: vedic mathematics. Journal of Indic Studies Foundation, CaliforniaGoogle Scholar
  8. 8.
    Chakrabarty, S.M., Kolluru, R..: Enjoy vedic mathematics. The Art of Living (Diamond Books), 31 Oct 2010Google Scholar
  9. 9.
    Parhi, K.K.: VLSI Digital Signal Processing Systems: Design and Implementation. Wiley, London (1999)Google Scholar
  10. 10.
    Morris Mano, M.: Computer System Architecture, 3rd edn, pp. 346–348. Prentice-Hall, New Jersey (1993)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringUniversity of Engineering and ManagementJaipurIndia
  2. 2.Department of Computer Science and EngineeringUniversity of Engineering and ManagementJaipurIndia

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