Dynamic Reconfigurable Architectures—A Boon for Desires of Real Time Systems

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 340)

Abstract

Speed of system, adaptability in runtime, short system response time, tolerance for faults, low latency in packet delivery, effective utilisation of on chip hardware resources and bandwidth with desired functionality execution are essential for real time applications. Analysis of competitive reliable reconfigurable architectures in distinct applications like image processing and performance up gradation in Discrete Cosine Transform (DCT), System on Chip (SoC), Network on Chip (NoC), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA) is done. The analysis described for reconfigurable architectures like Synthesis and Partitioning for Adaptive Reconfigurable Computing System (SPARCS), Course-Grained Reconfigurable Architectures (CGRAs), Multi Processors System on chip (MPSoC), North-last-weave algorithm, Sequential Minimal Optimization (SMO) algorithm have efficacy in achieving above mentioned desires of a real time electronic system.

Keywords

DRA MpSoC NoC SoC CGRA MUX DCT 

References

  1. 1.
    Huriaux, C., Sentieys, O., Tessier, R.: FPGA architecture enhancements to support heterogeneous partially reconfigurable regions. In: IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 30–30, May (2014)Google Scholar
  2. 2.
    Adario, A., Roehe, E., Bampi, S.: Dynamically reconfigurable architecture for image processor applications. In: Design Automation Conference, 1999. 36th Proceedings, pp. 623–628 (1999)Google Scholar
  3. 3.
    Borkute, C., Deshmukh, A., Kharkar, C.: Dynamic partial reconfiguration in FPGAs for DSP applications. In: 4th International Conference on Emerging Trends in Engineering and Technology (ICETET), pp. 253–257, Nov 2011Google Scholar
  4. 4.
    Wu, L.-W., Tang, W.-X., Hsu, Y.: A novel architecture and routing algorithm for dynamic reconfigurable network-on-chip. In: IEEE 9th International Symposium on Parallel and Distributed Processing with Applications (ISPA), pp. 177–182 (2011)Google Scholar
  5. 5.
    Fiack, L., Miramond, B., Upegui, A., Vannel, F.: Dynamic parallel reconfiguration for self-adaptive hardware architectures. In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 218–224, July 2014Google Scholar
  6. 6.
    Govindarajan, S., Ouaiss, I., Kaul, M., Srinivasan, V., Vemuri, R.: An effective design system for dynamically reconfigurable architectures. In: IEEE Symposium on FPGAs for Custom Computing Machines. Proceedings, pp. 312–313 (1998)Google Scholar
  7. 7.
    Peng, C.-H., Chen, B.-W., Kuan, T.-W., Lin, P.-C., Wang, J.-F., Shih, N.-S.: REC-STA: Reconfigurable and efficient chip design with SMO-based training accelerator, pp. 1–1 (2013)Google Scholar
  8. 8.
    Harada, S., Bai, X., Kameyama, M., Fujioka, Y.: Design of a logic-in-memory multiple-valued reconfigurable vlsi based on a bit-serial packet data transfer scheme. In: IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL), pp. 214–219, May 2014Google Scholar
  9. 9.
    Hussien, A., Amin, R., Eltawil, A., Martin, J.: Energy aware mapping for reconfigurable wireless MPSoCs, pp. 1–1 (2014)Google Scholar
  10. 10.
    Kao, C.-C.: Performance-oriented partitioning for task scheduling of parallel reconfigurable architectures, pp. 1–1 (2014)Google Scholar
  11. 11.
    Lin, T.-J., Zhang, W., Jha, N.: A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps, pp. 1–1, 2014Google Scholar
  12. 12.
    Shen, S., Hsiung, P.-A.: Reasoning and learning-based dynamic codec reconfiguration for varying processing requirements in network on-chip. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(8), 1777–1790 (2014)CrossRefGoogle Scholar
  13. 13.
    Vucha, M., Rajawat, A.: An effective dynamic scheduler for reconfigurable high speed computing system. In: IEEE International Advance Computing Conference (IACC), pp. 766–773, Feb 2014Google Scholar
  14. 14.
    Kim, Y., Mahapatra, R.: Dynamic context compression for low-power coarse-grained reconfigurable architecture. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(1), 15–28 (2010)CrossRefGoogle Scholar
  15. 15.
    Liu, Y., Dai, P., Wang, X., Zhang, X., Wei, L., Zhou, Y., Sun, Y.: Dynamic context management for coarse-grained reconfigurable array DSP architecture. In: IEEE 8th International Conference on ASIC. ASICON ’09, pp. 79–82Google Scholar
  16. 16.
    Rodriguez, J., Ackermann, K.: Leveraging partial dynamic reconfiguration on ZYNQ soc FPGAS. In: 9th International Symposium on Reconfigurable and Communication Centric Systems-on-Chip (ReCoSoC), pp. 1–6, May 2014Google Scholar
  17. 17.
    Pham, H., Devaux, L., Pillement, S.: Re2da: Reliable and reconfigurable dynamic architecture. In: 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011. Proceedings, 2011 [Online]. Available at www.scopus.com

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.VLSI Design, SENSEVIT UniversityVelloreIndia

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