Dynamic Reconfigurable Architectures—A Boon for Desires of Real Time Systems

  • Kevin Kansagara
  • K V Shravya
  • S Sivanantham
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 340)


Speed of system, adaptability in runtime, short system response time, tolerance for faults, low latency in packet delivery, effective utilisation of on chip hardware resources and bandwidth with desired functionality execution are essential for real time applications. Analysis of competitive reliable reconfigurable architectures in distinct applications like image processing and performance up gradation in Discrete Cosine Transform (DCT), System on Chip (SoC), Network on Chip (NoC), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA) is done. The analysis described for reconfigurable architectures like Synthesis and Partitioning for Adaptive Reconfigurable Computing System (SPARCS), Course-Grained Reconfigurable Architectures (CGRAs), Multi Processors System on chip (MPSoC), North-last-weave algorithm, Sequential Minimal Optimization (SMO) algorithm have efficacy in achieving above mentioned desires of a real time electronic system.




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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.VLSI Design, SENSEVIT UniversityVelloreIndia

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