Empirical Analysis of Low Power and High Performance Multiplier

Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 32)

Abstract

In this paper, A Modified Booth Recoding with Zero Bypassing technique for Low Power and High Performance Multiplier is proposed. In CMOS digital circuit design, the power and area are the main concerns. The proposed multiplier reduces the area and power consumption compared to the existing multipliers. In this paper, modified booth recoding technique and Encoder circuit and Zero bypassing Techniques are used. In this proposed multiplier, the numbers of partial products are reduced by using booth recoding with zero bypassing technique. The proposed multiplier is simulated and synthesized by using Xilinx 10.1 ISE design tool. The Total power is calculated by using XPower Analyzer.

Keywords

Switching activity reduction Booth recoding Full adder Zero bypassing 

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Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Department of E.C.EGMR Institute of TechnologyRajamIndia

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