Empirical Analysis of Low Power and High Performance Multiplier

Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 32)


In this paper, A Modified Booth Recoding with Zero Bypassing technique for Low Power and High Performance Multiplier is proposed. In CMOS digital circuit design, the power and area are the main concerns. The proposed multiplier reduces the area and power consumption compared to the existing multipliers. In this paper, modified booth recoding technique and Encoder circuit and Zero bypassing Techniques are used. In this proposed multiplier, the numbers of partial products are reduced by using booth recoding with zero bypassing technique. The proposed multiplier is simulated and synthesized by using Xilinx 10.1 ISE design tool. The Total power is calculated by using XPower Analyzer.


Switching activity reduction Booth recoding Full adder Zero bypassing 


  1. 1.
    Chandrakasan, A., Brodersen, R.: Low-power CMOS digital design. IEEE J. Solid- State Circ. 27(4), 473–484 (1992)CrossRefGoogle Scholar
  2. 2.
    Chen, O.T., Wang, S., Yi-Wen, Wu: Minimization of switching activities of partial products for designing low-power multipliers. IEEE Trans. VLSI Syst. 11, 418–433 (2003)CrossRefGoogle Scholar
  3. 3.
    Kuang, S.: Design of power-efficient configurable booth multiplier. IEEE Trans. circ. syst., 57(3), 568–580 (2010)Google Scholar
  4. 4.
    He, Y., Chang, C.: A new redundant binary booth encoding for fast 2n-bit multiplier design. IEEE Trans. Circ. Syst., 56(6), (2009)Google Scholar
  5. 5.
    Wu, A.: High performance adder cell for low power pipelined multiplier. IEEE Int. Symp. Circuits Syst. 4, 57–60 (1996)Google Scholar
  6. 6.
    Juang, T.B., Hsiao, S.F.: Low-power carry-free fixed-width multipliers with low-cost compensation circuit. IEEE Trans. 5 Circuits Syst. II Analog Digital Signal Process 52(6), 299–303 (2005)CrossRefMathSciNetGoogle Scholar
  7. 7.
    Kim, J.M., Lee, J.S., Cho, J.D.: A low power booth multiplier based on operand swapping in instruction level. J. Korean Phys. Soc., 33, S258–S261 (1998)Google Scholar
  8. 8.
    Devi V., Lokku, G.K., Natarajan, A.: Fixed width booth multiplier based on peb circuit. Int. J. Artificial Intell. Appl. (IJAIA), 3(2), 255–259 (2012)Google Scholar
  9. 9.
    Mottaghi-Dastjerdi, M., Afzali-Kusha, A., Pedram, M.: BZ-FAD- A low-power low-area multiplier based on shift-and-add architecture. IEEE Transactions on very large scale integration (VLSI) systems, vol. 17, no. 2 pp. 302–306 (February 2009)Google Scholar

Copyright information

© Springer India 2015

Authors and Affiliations

  1. 1.Department of E.C.EGMR Institute of TechnologyRajamIndia

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