Realization of Digital Down Convertor Using Xilinx System Generator

  • Manoj Kumar Sahoo
  • Kaliprasanna Swain
  • Amiya Kumar Rath
Conference paper
Part of the Smart Innovation, Systems and Technologies book series (SIST, volume 31)

Abstract

In some secure communication system, to detect the frequently varied baseband signal, a digital down converter (DDC) with a variable digital filter is used. In this paper, a reconfiguration design process of DDC is discussed for a GSM application with the help of Xilinx system generator (XSG) on field programmable gate array (FPGA). The approach is based on hardware Co-simulation based on XSG platform which integrates itself with the Matlab based Simulink graphics environment and implemented on Virtex-II based xc2v200-4fg676 FPGA device. Optimal equiripple technique implements DDC which reduces the resource requirement. To solve the complexity, a novel type of polyphase decomposition structure is used. Keeping the view of the system performance, such as area and speed, this paper proposes a model which is implemented by using embedded multiplier, LUTs and BRAM of FPGA. It is seen that the proposed design consumes very less resources available on target devices.

Keywords

DDC FPGA Matlab Xilinx system generator Co-HW simulation 

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Copyright information

© Springer India 2015

Authors and Affiliations

  • Manoj Kumar Sahoo
    • 1
  • Kaliprasanna Swain
    • 1
  • Amiya Kumar Rath
    • 2
  1. 1.GITAMadanpur, BhubaneswarIndia
  2. 2.VSSUTBurlaIndia

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